KR100189727B1 - Expansion of active area and isolation of semiconductor devices - Google Patents
Expansion of active area and isolation of semiconductor devices Download PDFInfo
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- KR100189727B1 KR100189727B1 KR1019910018131A KR910018131A KR100189727B1 KR 100189727 B1 KR100189727 B1 KR 100189727B1 KR 1019910018131 A KR1019910018131 A KR 1019910018131A KR 910018131 A KR910018131 A KR 910018131A KR 100189727 B1 KR100189727 B1 KR 100189727B1
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- oxide film
- isolation
- active area
- field
- field oxide
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
- H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/60—Wet etching
- H10P50/64—Wet etching of semiconductor materials
- H10P50/642—Chemical etching
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Abstract
본 발명은 반도체 제조공정에 관한 것으로서 특히 MOS소자에 적당하도록 액티브 영역확대 및 소자격리기술에 관한 것이다. 이를 위하여 본 발명에서는, 반도체 소자의 액티브 영역확대 및 소자격리 방법에 있어서, 실리콘 기판 상에 두꺼운 필드 산화막을 형성한 뒤 HF를 이용하여 습식에치백을 실시하므로 소자간을 격리하고 이로인해 액티브 영역의 둥근 면을 이루며 위로 솟아 면적의 확장효과를 얻을 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing process, and more particularly, to an active area enlargement and device isolation technology suitable for MOS devices. To this end, in the present invention, in the method for enlarging and isolating an active region of a semiconductor device, a thick field oxide film is formed on a silicon substrate, and wet etch back is performed using HF to isolate the devices and thereby It forms a rounded surface and rises up to obtain an area expansion effect.
Description
제1도는 종래 기술의 반도체 셀 제조 공정도1 is a process diagram of manufacturing a semiconductor cell of the prior art.
제2도는 본 발명의 반도체 셀 제조 공정도2 is a process diagram of manufacturing a semiconductor cell of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : 질화막1: silicon substrate 2: nitride film
3 : 필드 산화막 4 : 폴리실리콘3: field oxide film 4: polysilicon
5 : 캡 산화막 6 : 산화막5: cap oxide film 6: oxide film
7 : 산화막 8 : 폴리실리콘7: oxide film 8: polysilicon
9 : ONO 10 : 폴리실리콘 플레이트9: ONO 10: Polysilicon Plate
11 : BPSG 12 : 워드라인11: BPSG 12: Wordline
본 발명은 반도체 제조공정에 관한 것으로서 특히 MOS 소자에 적당하도록 액티브 영역확대 및 소자격리방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing process, and more particularly, to an active area enlargement and device isolation method suitable for MOS devices.
반도체 소자의 고집적화에 따라 대두되는 문제중에 규격 축소로 인한 소자간 격리 및 액티브 면적제한 등의 문제가 있다. 이를 해결하기 위해서 종래에는 격리기술로서는 트랜치 격리방법과 그 이전부터 가장 보편적으로 사용되는 LOCOS를 이용한 필드산화막 격리방법이 있다.Among the problems that arise due to the high integration of semiconductor devices, there are problems such as isolation between devices and active area limitations due to shrinking specifications. In order to solve this problem, conventional isolation techniques include a trench isolation method and a field oxide isolation method using LOCOS, which is the most commonly used method since then.
트랜치 격리는 실리콘 기판에 깊은 트랜치를 형성하여 소자간의 분리를 시도한 것이다. LOCOS라 함은 액티브 영역이 될 부분에 질화막(Si3N4)을 패터닝 한 뒤 열 산화를 하면 질화막 밑의 액티브 영역을 제외한 필드부에 두꺼운 산화막이 형성됨으로써 소자 격리 효과를 얻는 것이다.Trench isolation attempts to isolate devices by forming deep trenches in silicon substrates. LOCOS refers to a device isolation effect by forming a thick oxide film on the field portion except for the active region under the nitride film by thermal oxidation after patterning the nitride film (Si 3 N 4 ) in the active region.
이를 첨부된 도면 제1도를 참조하여 설명하면 다음과 같다.This will be described with reference to FIG. 1 of the accompanying drawings.
LOCOS 격리를 이용하는 경우 질화막 밑으로의 측면 확산에 의해 버즈비크가 생겨 액티브 영역을 잠식함으로써 액티브 면적이 줄어들게 되며 LOCOS 격리로써는 완벽한 소자 분리가 불가능하여 필드 산화전에 채널 스톱 이온주입을 사용하게 된다.When LOCOS isolation is used, lateral diffusion under the nitride film creates a buzz beating the active area, which reduces the active area. LOCOS isolation does not allow perfect device isolation, and channel stop ion implantation is used before field oxidation.
공정의 진행순서를 보면 먼저 제1도의 (a)와 같이 실리콘 기판위에 액티브 영역을 정의하고 채널스톱 이온주입을 실시한다. 계속해서 제1도의 (b)와 같이 필드산화(LOCOS)를 수행한다. 제 1도의 (c)와 같이 폴리실리콘을 데포지션하고 캡 산화막을 데포지션한다. 그후 게이트를 정의하여 LDD(Lightly Doped Drain)이온 주입을 실시한다. 이 때 주입 이온은 As+를 사용한다. 계속해서 제1도의 (d)와 같이 스페이서 산화막 데포지션을 실시하며, LDD에치를 수행하여 스페이서를 형성한다. 이어서 N+이온주입을 실시한다.In the process sequence, first, as shown in FIG. 1A, an active region is defined on a silicon substrate, and channel stop ion implantation is performed. Subsequently, field oxidation (LOCOS) is performed as shown in FIG. Polysilicon is deposited and the cap oxide film is deposited as shown in FIG. After that, the gate is defined to perform LDD (Lightly Doped Drain) ion implantation. In this case, As + is used as the implanted ion. Subsequently, spacer oxide film deposition is performed as shown in FIG. 1 (d), and LDD etching is performed to form a spacer. Subsequently, N + ion implantation is performed.
그 후 제1도의 (e)와 같이 베리드 콘택을 위한 산화막 데포지션을 실시한다.Thereafter, as shown in FIG. 1E, oxide deposition for buried contacts is performed.
그 후 제1도의 (f)와 같이 베리드 콘택 정의, 노드 폴리실리콘 데포지션 및 정의 데포지션 플레이트 폴리실리콘 데포지션, BPSG 막 데포지션 및 콘택정의, 워드라인 형성의 공정을 거쳐서 메로리 셀을 완성한다.Then, as shown in (f) of FIG. 1, the memory cell is completed through the process of buried contact definition, node polysilicon deposition and positive deposition plate polysilicon deposition, BPSG film deposition and contact definition, and word line formation. .
이러한 종래 기술에서는 필드 산화막형성시 버즈비크에 의한 액티브 면적감소를 감수해야하며 완전한 소자격리가 불가능하여 채널 스톱 이온주입 공정이 필요하다는 문제점이 있다.In the prior art, there is a problem in that an active area reduction by Buzzbee is required to form a field oxide film and a channel stop ion implantation process is required because complete device isolation is impossible.
본 발명은 이와같은 문제점을 시정, 보완하기 위해 안출된 것이다.The present invention has been made to correct and compensate for such a problem.
본 발명에서는 LOCOS를 이용하여 종래보다 훨씬 두꺼운 필드 산화막을 형성한 뒤 습식식각의 높은 선택비를 이용하여 에치 백을 실시하여 원하는 두께 만큼의 필드 산화막을 남긴다. 이때 필드 산화막의 두께는 종래보다 얇게하여도 액티브 영역이 위로 솟아있어서 효과적인 격리가 되며 또한 채널 스톱이온주입을 실시하지 않아도 된다.In the present invention, a much thicker field oxide film is formed by using LOCOS and then etched back using a high selectivity of wet etching to leave a field oxide film having a desired thickness. At this time, even if the thickness of the field oxide film is thinner than the conventional one, the active region is raised upward, so that effective isolation is achieved, and channel stop ion injection does not need to be performed.
본 발명을 첨부된 도면 제2도를 참조하여 설명하면 다음과 같다.Hereinafter, the present invention will be described with reference to FIG. 2.
먼저 제2도의 (a)와 같이 질화막(2)(Si3N4)으로 액티브 영역을 정의하고 (b)와 같이 필드산화막(3)을 형성한다.(LOCOS)First, the active region is defined by the nitride film 2 (Si 3 N 4 ) as shown in FIG. 2A, and the field oxide film 3 is formed as shown in (b) (LOCOS).
이어서 제2도의 (c)와 같이 습식에치 백을 하고(HF) 폴리실리콘(4) 및 캡 산화막(5)을 데포지션하고 게이트를 정의한다. 그 후 이온 주입(As)을 실시한다. 이어서 (d)와 같이 스페이서 산화막(6)을 데포지션하고 드라이에치백으로 스페이서를 형성하고 N+이온주입을 실시한다.Subsequently, a wet etch back (HF) is deposited (HF) as shown in FIG. After that, ion implantation (As) is performed. Subsequently, the spacer oxide film 6 is deposited as shown in (d), a spacer is formed by dry etching back, and N + ion implantation is performed.
계속해서 (e)와 같이 베리드 콘택용 산화막(7)을 데포지션한다. 제2도의 (f)는 본 발명의 완성도로서 계속되는 공정은 베리드 콘택을 정의하고, 노드 폴리실리콘(8)을 데포지션 한 후, 이온주입 및 정의 단계와, ONO(9)를 데포지션하는 단계, 폴리실리콘 플레이트(10)을 데포지션하는 단계, BPSG(11) 데포지션 및 콘택 정의단계, 워드라인(12) 형성단계로서 종래의 단계와 같다.Subsequently, the buried contact oxide film 7 is deposited as shown in (e). FIG. 2 (f) shows that the process which is continued as the completeness of the present invention defines a buried contact, deposits the node polysilicon 8, ion implantation and definition steps, and deposits ONO 9 Deposition of the polysilicon plate 10, BPSG (11) deposition and contact definition step, the word line 12 forming step is the same as the conventional step.
이와같이 본 발명의 방법을 사용하므로, 즉 필드 산화막을 두껍게 성장한 뒤 습식 에치 백을 실시함으로써 액티브영역이 둥근 원형을 가지고 필드산화막 보다 높게 위로 솟아 있게 되고 트랜치와 같은 격리를 할 수 있어 BF2I/I등의 채널 스톱 I/I가 필요없으며, 기존의 필드 산화막보다 두께가 얇아도 되므로 액티브 면적의 이득을 얻을 수 있고 평면보다 확장된 곡면을 액티브로 사용하므로 상대적인 면적 확장을 가할 수 있어서 고집적과 소자의 팩킹밀도를 높일 수 있으며, 효과적으로 격리된 MOS를 제조할 수 있다.Thus, by using the method of the present invention, that is, by thickly growing the field oxide film and performing a wet etch back, the active region has a rounded shape and rises higher than the field oxide film and can be isolated like a trench so that BF 2 I / I No channel stop I / I, etc. is required, and the thickness can be thinner than the existing field oxide film, and the gain of the active area can be obtained, and the curved area extended than the plane is used as active, so that the relative area can be extended. It is possible to increase the packing density and to produce an effectively isolated MOS.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910018131A KR100189727B1 (en) | 1991-10-15 | 1991-10-15 | Expansion of active area and isolation of semiconductor devices |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910018131A KR100189727B1 (en) | 1991-10-15 | 1991-10-15 | Expansion of active area and isolation of semiconductor devices |
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| Publication Number | Publication Date |
|---|---|
| KR930009059A KR930009059A (en) | 1993-05-22 |
| KR100189727B1 true KR100189727B1 (en) | 1999-06-01 |
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| KR1019910018131A Expired - Fee Related KR100189727B1 (en) | 1991-10-15 | 1991-10-15 | Expansion of active area and isolation of semiconductor devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9184232B2 (en) | 2003-05-28 | 2015-11-10 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
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| JP4592193B2 (en) * | 2001-02-06 | 2010-12-01 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9184232B2 (en) | 2003-05-28 | 2015-11-10 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
| US9263588B2 (en) | 2003-05-28 | 2016-02-16 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
| US9595612B2 (en) | 2003-05-28 | 2017-03-14 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
| US9847422B2 (en) | 2003-05-28 | 2017-12-19 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
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| Publication number | Publication date |
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| KR930009059A (en) | 1993-05-22 |
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