KR20020002007A - A method for forming a contact hole of a semiconductor device - Google Patents
A method for forming a contact hole of a semiconductor device Download PDFInfo
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- KR20020002007A KR20020002007A KR1020000036400A KR20000036400A KR20020002007A KR 20020002007 A KR20020002007 A KR 20020002007A KR 1020000036400 A KR1020000036400 A KR 1020000036400A KR 20000036400 A KR20000036400 A KR 20000036400A KR 20020002007 A KR20020002007 A KR 20020002007A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
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Abstract
본 발명은 반도체 소자의 콘택홀 형성방법에 관한 것으로, 콘택홀 형성 후 상기 콘택홀의 측벽과 반도체기판의 접합영역과 소자분리절연막의 계면에 절연막 스페이서를 형성함으로써 콘택영역이 반도체기판의 활성영역보다 낮은 부분에 형성되는 것을 방지하여 접합누설전류 특성을 향상시켜 소자의 동작특성 및 신뢰성을 향상시키는 기술에 관한 것이다.The present invention relates to a method for forming a contact hole in a semiconductor device, wherein after forming the contact hole, an insulating layer spacer is formed at an interface between the sidewall of the contact hole, the junction region of the semiconductor substrate, and the device isolation insulating film, whereby the contact region is lower than the active region of the semiconductor substrate. The present invention relates to a technique for preventing the formation of a portion to improve the junction leakage current characteristic to improve the operation characteristics and reliability of the device.
Description
본 발명은 반도체 소자의 콘택홀 형성방법에 관한 것으로, 특히 콘택홀 형성 시 반도체기판의 접합영역과의 미스얼라인(misalignment)에 의해 소자분리절연막이 손실되어 콘택영역이 상기 활성영역보다 낮게 형성되는 것을 방지하는 반도체소자의 콘택홀 형성방법에 관한 것이다.The present invention relates to a method for forming a contact hole in a semiconductor device. In particular, when a contact hole is formed, a device isolation insulating film is lost due to misalignment with a junction region of a semiconductor substrate, whereby the contact region is formed lower than the active region. The present invention relates to a method for forming a contact hole in a semiconductor device for preventing the same.
일반적으로, 반도체 소자에서 상하의 도전배선을 연결하는 콘택홀은 자체의 크기와 주변 배선과의 간격이 감소되고, 콘택홀의 지름과 깊이의 비인 에스팩트비(aspect ratio)는 증가한다.In general, the contact hole connecting the upper and lower conductive wirings in the semiconductor device is reduced in size and the distance between the peripheral wiring and the aspect ratio, which is the ratio of the diameter and the depth of the contact hole, is increased.
따라서, 다층의 도전배선을 구비하는 고집적 반도체소자에서는 콘택을 형성하기 위하여 제조 공정에서의 마스크들간의 정확하고 엄격한 정렬이 요구되어 공정여유도가 감소된다.Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.
상기 콘택홀은 간격 유지를 위하여 마스크 정렬시의 미스얼라인먼트 여유(misalignment tolerance), 노광 공정 시의 렌즈 왜곡(lens distortion), 마스크 제작 및 사진식각 공정시의 임계크기 변화(critical dimension variation), 마스크간의 정합(registration)등과 같은 요인들을 고려하여 마스크를 형성한다.The contact hole has misalignment tolerance during mask alignment, lens distortion during exposure process, critical dimension variation during mask fabrication and photolithography process, and between masks to maintain spacing. The mask is formed by considering factors such as registration.
또한, 콘택홀 형성 시 리소그래피(Lithography) 공정의 한계를 극복하기 위하여 자기 정렬 콘택홀(self aligned contact : 이하 SAC라 칭함) 형성 기술이 개발되었다.In addition, in order to overcome the limitations of a lithography process in forming a contact hole, a self-aligned contact hole (hereinafter referred to as SAC) formation technology has been developed.
이하, 첨부된 도면을 참고로 하여 종래기술에 따른 반도체소자의 콘택홀 형성방법을 설명한다.Hereinafter, a method for forming a contact hole in a semiconductor device according to the related art will be described with reference to the accompanying drawings.
도 1 은 종래기술에 따른 반도체소자의 콘택홀 형성방법의 문제점을 도시한 단면도이다.1 is a cross-sectional view illustrating a problem of a method for forming a contact hole in a semiconductor device according to the prior art.
먼저, 반도체기판(10)에서 소자분리영역으로 예정되는 부분에 소자분리절연막(11)을 형성하고, 활성영역 상에 게이트절연막패턴(12)과 게이트전극(13)을 형성한다.First, a device isolation insulating film 11 is formed in a portion of the semiconductor substrate 10 that is intended as a device isolation region, and a gate insulating film pattern 12 and a gate electrode 13 are formed on the active region.
다음, 상기 게이트전극(13)의 양측 반도체기판(10)에 불순물이온을 주입하여 소오스/드레인영역으로 되는 접합영역(14)을 형성한다.Next, impurity ions are implanted into both semiconductor substrates 10 of the gate electrode 13 to form a junction region 14 serving as a source / drain region.
그 다음, 전체표면 상부에 금속배선 콘택으로 예정되는 부분을 노출시키는 콘택홀이 구비된 층간절연막(15)을 형성하고, 상기 콘택홀을 통하여 상기 접합영역(14)에 접속되는 금속배선(16)을 형성한다.Next, an interlayer insulating film 15 having a contact hole exposing a portion intended as a metal wiring contact is formed on the entire surface, and the metal wiring 16 connected to the junction region 14 through the contact hole. To form.
여기서, 상기 콘택홀을 형성하기 위한 식각공정 시 미스얼라인먼트에 의해 상기 접합영역(14)에서 벗어난 소자분리절연막(11)이 식각되고, 특히 ⓧ부분과 같이 접합영역(14)과 금속배선(16)이 만나는 부분이 활성영역 표면보다 더 깊게 들어가서 접합누설전류를 증가시키고, 그로 인하여 활성영역을 줄이기 위해 활성영역과 소자분리영역 사이의 간격을 줄이거나 없애는 경우 심각한 문제점이 발생한다.Here, the element isolation insulating film 11 deviated from the junction region 14 by the misalignment during the etching process for forming the contact hole is etched, and in particular, the junction region 14 and the metal wiring 16 are formed as shown in FIG. Serious problems arise when the junctions go deeper than the active area surface to increase the junction leakage current, thereby reducing or eliminating the gap between the active area and the device isolation area to reduce the active area.
도 2a 내지 도 2f 는 상기 문제점을 해결하기 위한 반도체소자의 콘택홀 형성방법을 도시한 단면도이다.2A to 2F are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device for solving the above problem.
먼저, 반도체기판(20) 상부에 상기와 같은 방법으로 소자분리절연막(21), 게이트절연막(22), 게이트전극(23) 및 접합영역(24)을 형성하고, 전체표면 상부에 질화막을 소정 두께 형성하여 식각방지막(25)을 형성한다. (도 2a, 도 2b 참조)First, the device isolation insulating film 21, the gate insulating film 22, the gate electrode 23, and the junction region 24 are formed on the semiconductor substrate 20 in the same manner as above, and the nitride film is formed on the entire surface by a predetermined thickness. To form an etch stop layer 25. (See FIG. 2A, FIG. 2B)
다음, 상기 식각방지막(25) 상부에 산화막으로 층간절연막(26)을 형성한다. (도 2c 참조)Next, an interlayer insulating layer 26 is formed of an oxide layer on the etch stop layer 25. (See Figure 2c)
그 다음, 상기 접합영역(24)에서 콘택으로 예정되는 부분을 노출시키는 콘택마스크를 식각마스크로 상기 층간절연막(25)을 식각하여 콘택홀(27)을 형성한다. (도 2d 참조)Thereafter, the interlayer insulating layer 25 is etched using a contact mask that exposes a portion of the junction region 24, which is supposed to be a contact, to form a contact hole 27. (See FIG. 2D)
다음, 상기 콘택홀(27) 저부에 노출되는 식각방지막(25)을 제거한다. (도 2e 참조)Next, the etch stop layer 25 exposed to the bottom of the contact hole 27 is removed. (See Figure 2E)
그 다음, 상기 콘택홀(27)을 통하여 상기 접합영역(24)에 접속되는 금속배선(28)을 형성한다. (도 2f 참조)Next, a metal wiring 28 connected to the junction region 24 through the contact hole 27 is formed. (See Figure 2f)
상기와 같은 종래 기술에 따르면 콘택홀 형성 시 층간절연막을 형성하기 전에 식각방지막을 형성하여 소자분리절연막이 식각되는 것을 방지하여 콘택이 깊게 형성되는 것을 방지할 수는 있지만, 2번의 식각공정에 의해 콘택홀을 형성해야 하는 번거로움이 있고, 소자분리절연막이 손실되는 것을 방지할 수 있으나, 상기 소자분리절연막이 활성영역보다 낮게 형성되는 경우 활성영역과 소자분리절연막의 경계면인 ⓨ부분에서 콘택이 활성영역보다 낮게 형성되어 소자의 리프레쉬 특성을 저하시키는 문제점이 있다.According to the prior art as described above, the formation of an etch stop layer before forming the interlayer insulating layer to form a contact hole to prevent the device isolation insulating layer from being etched to prevent the formation of a deep contact, but the contact by the two etching process Although it is troublesome to form a hole, and the device isolation insulating film can be prevented from being lost, when the device isolation insulating film is formed lower than the active area, the contact is active at the ⓨ part which is an interface between the active area and the device isolation insulating film. There is a problem that the lower the lower the refresh characteristics of the device.
본 발명은 상기한 문제점을 해결하기 위한 것으로 반도체기판에 소자분리절연막을 형성하고, 반도체기판의 활성영역에 게이트전극과 소오스/드레인 접합영역을 형성한 다음, 전체표면 상부에 층간절연막을 형성하고, 상기 접합영역에서 콘택으로 예정되는 부분을 노출시키는 콘택마스크를 식각마스크로 상기 층간절연막을 식각하여 콘택홀을 형성한 후 상기 콘택홀의 측벽 및 상기 콘택홀을 형성하기 위한 식각공정으로 노출되는 접합영역의 측벽에 절연막 스페이서를 형성함으로써 접합누설전류 특성을 개선하여 소자의 동작 특성 및 신뢰성을 향상시키는 반도체 소자의 콘택홀 형성방법을 제공하는데 그 목적이 있다.The present invention is to solve the above problems to form a device isolation insulating film on a semiconductor substrate, a gate electrode and a source / drain junction region in the active region of the semiconductor substrate, and then to form an interlayer insulating layer on the entire surface, After forming a contact hole by etching the interlayer insulating layer by using a contact mask that exposes a predetermined portion of the contact portion as an etch mask in the junction region, a sidewall of the contact hole and an etching process for forming the contact hole are exposed. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a contact hole in a semiconductor device by forming an insulating film spacer on a sidewall, thereby improving junction leakage current characteristics, thereby improving operation characteristics and reliability of the device.
도 1 은 종래기술에 따른 반도체소자의 콘택홀 형성방법의 문제점을 도시한 단면도.1 is a cross-sectional view showing a problem of a method for forming a contact hole in a semiconductor device according to the prior art.
도 2a 내지 도 2f 는 종래기술에 따른 문제점을 해결하기 위한 반도체소자의 제조방법을 도시한 단면도.2A to 2F are cross-sectional views showing a method of manufacturing a semiconductor device for solving the problems according to the prior art.
도 3a 내지 도 3e 는 본 발명에 따른 반도체소자의 콘택홀 형성방법을 도시한 단면도.3A to 3E are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device according to the present invention.
< 도면의 주요부분에 대한 부호의 설명><Description of the reference numerals for the main parts of the drawings>
10, 20, 30 : 반도체 기판 11, 21, 31 : 소자분리절연막10, 20, 30: semiconductor substrate 11, 21, 31: device isolation insulating film
12, 22, 32 : 게이트절연막 패턴 13, 23, 33 : 게이트전극12, 22, 32: gate insulating film pattern 13, 23, 33: gate electrode
14, 24, 34 : 접합영역 15, 26, 35 : 층간절연막14, 24, 34: junction region 15, 26, 35: interlayer insulating film
16, 28, 38 : 금속배선 25 : 식각방지막16, 28, 38: metal wiring 25: etching prevention film
27, 36 : 콘택홀 37a : 절연막27, 36: contact hole 37a: insulating film
37b : 절연막 스페이서37b: insulating film spacer
상기 목적을 달성하기 위해 본 발명에 따른 반도체 소자의 콘택홀 형성방법은,Contact hole forming method of a semiconductor device according to the present invention to achieve the above object,
반도체기판에서 소자분리영역으로 예정되는 부분에 소자분리절연막을 형성하고, 상기 반도체기판의 활성영역에 게이트절연막을 형성하는 공정과,Forming a device isolation insulating film in a portion of the semiconductor substrate, which is intended as a device isolation region, and forming a gate insulating film in an active region of the semiconductor substrate;
상기 게이트절연막 상부에 게이트전극을 형성하고, 상기 게이트전극의 양측 반도체기판에 불순물이온을 주입하여 소오스/드레인 접합영역을 형성하는 공정과,Forming a gate electrode on the gate insulating layer, and implanting impurity ions into semiconductor substrates on both sides of the gate electrode to form a source / drain junction region;
전체표면 상부에 층간절연막을 형성하는 공정과,Forming an interlayer insulating film over the entire surface;
상기 접합영역에서 콘택으로 예정되는 부분을 노출시키는 콘택마스크를 식각마스크로 상기 층간절연막을 식각하여 콘택홀을 형성하는 공정과,Forming a contact hole by etching the interlayer insulating layer with an etch mask using a contact mask that exposes a predetermined portion of the contact in the junction region;
전체표면 상부에 소정 두께의 절연막을 형성하는 공정과,Forming an insulating film having a predetermined thickness over the entire surface;
상기 절연막을 전면식각하여 상기 콘택홀의 측벽에 절연막 스페이서를 형성하되, 미스얼라인이 발생되어 상기 소자분리절연막이 식각되어 상기 접합영역과 단차가 발생한 경우 상기 소자분리절연막과 접합영역의 경계면에도 절연막 스페이서를 형성하는 공정을 포함하는 것을 특징으로 한다.An insulating layer spacer is formed on the sidewall of the contact hole by etching the insulating layer on the entire surface of the contact hole, but when the misalignment occurs and the device isolation insulating layer is etched to generate the stepped portion and the junction region, the insulating layer spacer is formed on the interface between the isolation region and the junction region It characterized in that it comprises a step of forming a.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 콘택홀 형성방법에 대하여 상세히 설명을 하기로 한다.Hereinafter, a method of forming a contact hole in a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 도 3e 는 본 발명에 따른 반도체소자의 콘택홀 형성방법을 도시한 단면도이다.3A to 3E are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device according to the present invention.
먼저, 반도체기판(30)에서 소자분리영역으로 예정되는 부분에 소자분리절연막(31)을 형성한다.First, an element isolation insulating film 31 is formed on a portion of the semiconductor substrate 30 that is intended as an element isolation region.
다음, 상기 반도체기판(30)의 활성영역에 게이트절연막(도시 안됨) 및 게이트전극용 도전층(도시 안됨)을 형성하고, 게이트전극 마스크를 식각마스크로 상기 게이트전극용 도전층 및 게이트절연막을 식각하여 게이트전극(33)과 게이트절연막패턴(32)을 형성한다.Next, a gate insulating film (not shown) and a gate electrode conductive layer (not shown) are formed in the active region of the semiconductor substrate 30, and the gate electrode mask is etched using the gate electrode mask to etch the conductive layer and the gate insulating film. Thus, the gate electrode 33 and the gate insulating film pattern 32 are formed.
그 다음, 상기 게이트전극(33)의 양측 반도체기판(30)에 불순물이온을 주입하여 소오스/드레인 접합영역(34)을 형성한다.Next, impurity ions are implanted into both semiconductor substrates 30 of the gate electrode 33 to form a source / drain junction region 34.
다음, 전체표면 상부에 층간절연막(35)을 형성한다. (도 3a 참조)Next, an interlayer insulating film 35 is formed over the entire surface. (See Figure 3A)
그 다음, 상기 접합영역(34)에서 콘택으로 예정되는 부분을 노출시키는 콘택마스크(도시 안됨)를 식각마스크로 상기 층간절연막(35)을 식각하여 콘택홀(36)을 형성한다. 이때, 미스얼라인이 발생한 경우 상기 소자분리절연막(31)이 식각되어 상기 소자분리절연막(31)과 접합영역(34) 간에 단차가 발생하고, 그로 인하여 접합영역(34)이 노출된다. (도 3b 참조)Next, the contact hole 36 is formed by etching the interlayer insulating layer 35 using a contact mask (not shown) that exposes a portion of the junction region 34 to be a contact, as an etch mask. In this case, when a misalignment occurs, the device isolation insulating layer 31 is etched to generate a step between the device isolation insulating layer 31 and the junction region 34, thereby exposing the junction region 34. (See Figure 3b)
다음, 전체표면 상부에 상기 소자분리절연막(31)과 식각선택비차이를 갖는 절연막(37a)을 소정 두께 형성한다. 이때, 상기 절연막(37a)은 질화막으로 형성한다. (도 3c 참조)Next, an insulating film 37a having an etching selectivity difference with the device isolation insulating film 31 is formed on the entire surface. At this time, the insulating film 37a is formed of a nitride film. (See Figure 3c)
그 다음, 상기 절연막(37a)을 건식식각방법으로 전면식각하여 상기 콘택홀(36)의 측벽 및 상기 소자분리절연막(31)과 접합영역(34)의 경계면인 단차부분에 절연막 스페이서(37b)를 형성한다. (도 3d 참조)Next, the insulating layer 37a is entirely etched by a dry etching method, and the insulating layer spacer 37b is formed on the sidewall of the contact hole 36 and the stepped portion that is an interface between the device isolation insulating layer 31 and the junction region 34. Form. (See FIG. 3D)
다음, 전체표면 상부에 금속층(도시 안됨)을 형성하고, 금속배선 마스크를 식각마스크로 상기 금속층을 식각하여 상기 콘택홀(36)을 통하여 상기 접합영역(34)에접속되는 금속배선(38)을 형성한다. (도 3e 참조)Next, a metal layer (not shown) is formed on the entire surface, the metal layer is etched using a metal wiring mask as an etch mask, and the metal wiring 38 connected to the junction region 34 through the contact hole 36 is formed. Form. (See Figure 3E)
한편, 도 3f 는 콘택홀(36)을 형성하고 형성되는 절연막을 소자분리절연막(31)과 식각선택비 차이를 갖지 않는 산화막으로 형성한 경우를 도시한 것으로서, 절연막 스페이서(37b) 형성 시 소자분리절연막(31)이 ⓩ부분과 같이 다량 제거되더라도, 후속공정으로 형성되는 금속배선(38)의 콘택부분이 반도체기판(30)의 활성영역보다 낮게 형성되는 것을 방지할 수 있다.Meanwhile, FIG. 3F illustrates a case in which the contact hole 36 is formed and the insulating film formed is formed of an oxide film having no difference in etching selectivity from the device isolation insulating film 31, and the device is separated when the insulating film spacer 37b is formed. Even if the insulating film 31 is removed in a large amount, such as the concave portion, it is possible to prevent the contact portion of the metal wiring 38 formed in a subsequent process from being formed lower than the active region of the semiconductor substrate 30.
상기한 바와 같이 본 발명에 따르면, 콘택홀 형성 후 상기 콘택홀의 측벽과 반도체기판의 접합영역과 소자분리절연막의 계면에 절연막 스페이서를 형성함으로써 콘택영역이 반도체기판의 활성영역보다 낮은 부분에 형성되는 것을 방지하여 접합누설전류 특성을 개선하여 소자의 동작 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, according to the present invention, after the contact hole is formed, an insulating layer spacer is formed at the interface between the sidewall of the contact hole, the junction region of the semiconductor substrate and the device isolation insulating film to form the contact region at a lower portion than the active region of the semiconductor substrate. By preventing the improvement of the junction leakage current characteristics, there is an advantage to improve the operating characteristics and reliability of the device.
Claims (3)
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| KR1020000036400A KR20020002007A (en) | 2000-06-29 | 2000-06-29 | A method for forming a contact hole of a semiconductor device |
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| KR1020000036400A KR20020002007A (en) | 2000-06-29 | 2000-06-29 | A method for forming a contact hole of a semiconductor device |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0256954A (en) * | 1988-08-22 | 1990-02-26 | Seiko Epson Corp | semiconductor equipment |
| JP2000012687A (en) * | 1998-06-23 | 2000-01-14 | Mitsubishi Electric Corp | Semiconductor device and manufacturing method thereof |
| JP2000048017A (en) * | 1998-07-27 | 2000-02-18 | Sanyo Electric Co Ltd | Document processor |
| KR20000014736A (en) * | 1998-08-24 | 2000-03-15 | 김영환 | Semiconductor device and fabrication method thereof |
| JP2000174137A (en) * | 1998-12-08 | 2000-06-23 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
-
2000
- 2000-06-29 KR KR1020000036400A patent/KR20020002007A/en not_active Ceased
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0256954A (en) * | 1988-08-22 | 1990-02-26 | Seiko Epson Corp | semiconductor equipment |
| JP2000012687A (en) * | 1998-06-23 | 2000-01-14 | Mitsubishi Electric Corp | Semiconductor device and manufacturing method thereof |
| JP2000048017A (en) * | 1998-07-27 | 2000-02-18 | Sanyo Electric Co Ltd | Document processor |
| KR20000014736A (en) * | 1998-08-24 | 2000-03-15 | 김영환 | Semiconductor device and fabrication method thereof |
| JP2000174137A (en) * | 1998-12-08 | 2000-06-23 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
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