KR20020002700A - Method for forming metal line - Google Patents
Method for forming metal line Download PDFInfo
- Publication number
- KR20020002700A KR20020002700A KR1020000036952A KR20000036952A KR20020002700A KR 20020002700 A KR20020002700 A KR 20020002700A KR 1020000036952 A KR1020000036952 A KR 1020000036952A KR 20000036952 A KR20000036952 A KR 20000036952A KR 20020002700 A KR20020002700 A KR 20020002700A
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- South Korea
- Prior art keywords
- metal wiring
- contact hole
- forming
- layer
- lower portion
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
- H10W20/082—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being tapered via holes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 감광막 패턴(Pattern)을 마스크로 제 1 차 식각된 층간 절연막을 상기 측벽에 폴리머(Polymer)가 발생된 감광막 패턴을 마스크로 제 2 차 식각하여 그 하부부위가 포지티브 슬로프(Positive slope)의 식각 형상을 갖는 금속 배선 콘택홀을 형성하므로 금속 배선 형성 공정 시 상기 금속 배선 콘택홀 하부부위의 보이드(Void) 발생을 방지하기 위한 금속 배선 형성 방법에 관한 것이다.According to the present invention, the interlayer insulating film firstly etched using the photoresist pattern (Pattern) as a mask is secondly etched using the photoresist pattern in which the polymer is generated on the sidewalls as a mask, and a lower portion thereof is formed on the positive slope. Since a metal wiring contact hole having an etched shape is formed, the present invention relates to a metal wiring forming method for preventing voids in the lower portion of the metal wiring contact hole during a metal wiring forming process.
본 발명의 금속 배선 형성 방법은 감광막 패턴을 마스크로 제 1 차 식각된 층간 절연막을 상기 측벽에 폴리머가 발생된 감광막 패턴을 마스크로 제 2 차 식각하여 그 하부부위가 포지티브 슬로프의 식각 형상을 갖는 금속 배선 콘택홀을 형성하므로, 상기 금속 배선 콘택홀 하부부위에도 베리어(Barrier)층이 형성되어 금속 배선 형성층인 알루미늄층의 형성 공정 시 상기 금속 배선 콘택홀 하부부위의 보이드 발생을 방지하므로 금속 배선의 신뢰성을 향상시키는 특징이 있다.In the method of forming a metal wiring according to the present invention, the first interlayer insulating film etched with the photoresist pattern as a mask is secondly etched with the photoresist pattern with the polymer generated on the sidewalls as a mask, and a lower portion thereof has an etching shape of a positive slope. Since a wiring contact hole is formed, a barrier layer is formed on the lower portion of the metal wiring contact hole, thereby preventing voids in the lower portion of the metal wiring contact hole during the formation of an aluminum layer, which is a metal wiring forming layer, so that the reliability of the metal wiring is reduced. There is a feature to improve.
Description
본 발명은 금속 배선 형성 방법에 관한 것으로, 특히 하부부위가 포지티브 슬로프(Positive slope)의 식각 형상을 갖는 금속 배선 콘택홀을 형성하여 금속 배선의 신뢰성을 향상시키는 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings, and more particularly, to a metal wiring forming method for improving reliability of metal wirings by forming a metal wiring contact hole having an etched shape of a positive slope.
종래의 금속 배선 형성 방법은 도 1a에서와 같이, 반도체 기판(11)상에 제 1비피에스지(Boron Phosphrus Silicate Glass : BPSG)층(12), 아이피오(Inter Poly Oxide : IPO)층(13) 및 제 2 BPSG층(14)을 순차적으로 형성한다.A conventional metal wiring forming method is as shown in FIG. 1A, on the semiconductor substrate 11, a first BPSG layer 12 and an interpoly oxide (IPO) layer 13. And the second BPSG layer 14 are sequentially formed.
도 1b에서와 같이, 상기 제 2 BPSG층(14)상에 감광막(15)을 도포하고, 상기 감광막(15)을 금속 배선 콘택홀 형성될 부위에서만 제거되도록 선택적으로 노광 및 현상한다.As shown in FIG. 1B, a photoresist film 15 is coated on the second BPSG layer 14, and the photoresist film 15 is selectively exposed and developed to be removed only at a portion where a metal wiring contact hole is to be formed.
도 1c에서와 같이, 상기 선택적으로 노광 및 현상된 감광막(15)을 마스크로 상기 제 2 BPSG층(14), IPO층(13), BPSG층(12) 및 반도체 기판(11)을 선택 식각하여 금속 배선 콘택홀(16)을 형성한 후, 상기 감광막(15)을 제거한다.As shown in FIG. 1C, the second BPSG layer 14, the IPO layer 13, the BPSG layer 12, and the semiconductor substrate 11 are selectively etched using the selectively exposed and developed photosensitive film 15 as a mask. After the metal wiring contact hole 16 is formed, the photosensitive film 15 is removed.
여기서, 상기 금속 배선 콘택홀(16)의 하부부위가 네가티브(Negative) 슬로프의 식각 형상(A)을 갖는다.Here, the lower portion of the metal wiring contact hole 16 has an etched shape A of a negative slope.
도 1d에서와 같이, 상기 금속 배선 콘택홀(16)을 포함한 전면에 베리어(Barrier)층으로 티타늄(Ti)(17)층과 TiN층(18)을 순차적으로 형성한다.As shown in FIG. 1D, a titanium (Ti) layer 17 and a TiN layer 18 are sequentially formed as a barrier layer on the front surface including the metal wiring contact hole 16.
그리고, 상기 TiN층(18)상에 알루미늄(Al)층(19)을 형성한다.In addition, an aluminum (Al) layer 19 is formed on the TiN layer 18.
그러나 종래의 금속 배선 형성 방법은 금속 배선 콘택홀의 하부부위가 네가티브 슬로프의 식각 형상을 갖기 때문에 상기 금속 배선 콘택홀 하부부위에 베리어층이 형성되지 않아 금속 배선 형성층인 알루미늄층이 상기 금속 배선 콘택홀 하부부위까지 매립되지 않아 상기 금속 배선 콘택홀 하부부위에 보이드(Void)가 발생되므로 금속 배선의 신뢰성을 저하시키는 문제점이 있었다.However, in the conventional metal wiring forming method, since the lower portion of the metal wiring contact hole has an etched shape of a negative slope, a barrier layer is not formed on the lower portion of the metal wiring contact hole, so that an aluminum layer, which is a metal wiring forming layer, is formed under the metal wiring contact hole. Since voids are generated in the lower portion of the metal wiring contact hole because the portion is not buried, there is a problem of lowering the reliability of the metal wiring.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 감광막 패턴을 마스크로 제 1 차 식각된 층간 절연막을 상기 측벽에 폴리머(Polymer)가 발생된 감광막 패턴을 마스크로 제 2 차 식각하여 그 하부부위가 포지티브 슬로프의 식각 형상을 갖는 금속 배선 콘택홀을 형성하므로 금속 배선 형성층인 알루미늄층의 형성 공정 시 상기 금속 배선 콘택홀 하부부위의 보이드 발생을 방지하는 금속 배선 형성 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and the lower portion of the interlayer insulating film firstly etched using the photosensitive film pattern as a mask is secondly etched using the photosensitive film pattern having polymer generated on the sidewalls as a mask. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a metal wiring contact hole having an etched shape of a positive slope, thereby preventing voids in the lower portion of the metal wiring contact hole during a process of forming an aluminum layer, which is a metal wiring forming layer.
도 1a 내지 도 1d의 종래의 금속 배선 형성 방법을 나타낸 공정 단면도Process sectional view showing the conventional metal wiring forming method of FIGS. 1A to 1D
도 2a 내지 도 2e는 본 발명의 실시 예에 따른 금속 배선 형성 방법을 나타낸 공정 단면도2A through 2E are cross-sectional views illustrating a method of forming a metal wiring according to an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
31 : 반도체 기판 32 : 제 1 BPSG층31 semiconductor substrate 32 first BPSG layer
33 : IPO층 34 : 제 2 BPSG층33: IPO layer 34: second BPSG layer
35 : 감광막 36 : 금속 배선 트렌치35 photosensitive film 36 metal wiring trench
37 : 폴리머 측벽 38 : 금속 배선 콘택홀37 polymer sidewall 38 metal wiring contact hole
39 : Ti층 40 : TiN층39: Ti layer 40: TiN layer
본 발명의 금속 배선 형성 방법은 기판상에 제 1, 제 2, 제 3 절연막을 순차적으로 형성하는 단계, 상기 제 3 절연막상에 금속 배선 트렌치가 형성될 부위에서만 제거된 감광막 패턴을 형성하는 단계, 상기 감광막 패턴을 마스크로 상기 제 3 절연막과 제 2 절연막을 선택 식각하여 금속 배선 트렌치를 형성하는 단계, 상기 감광막 패턴 측면에 폴리머 측벽을 형성하는 단계, 상기 감광막과 폴리머 측벽을 마스크로 상기 제 1 절연막을 선택 식각하여 그 하부부위가 포지티브 슬로프의 식각 형상을 갖는 금속 배선 콘택홀을 형성하는 단계 및 상기 감광막과 폴리머 측벽을 제거하고, 상기 금속 배선 콘택홀을 포함한 전면에 베리어층을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.In the metal wire forming method of the present invention, the step of sequentially forming the first, second, third insulating film on the substrate, the step of forming a photoresist film pattern is removed only on the portion of the metal wiring trench to be formed on the third insulating film, Selectively etching the third insulating film and the second insulating film using the photoresist pattern as a mask to form a metal wiring trench, forming a polymer sidewall on a side of the photoresist pattern, and using the photoresist and the polymer sidewall as a mask, the first insulating film And selectively etching to form a metal interconnection contact hole having a lower portion thereof having an etched shape of a positive slope, and removing the photosensitive layer and the polymer sidewall, and forming a barrier layer on the front surface including the metal interconnection contact hole. Characterized in that made.
상기와 같은 본 발명에 따른 금속 배선 형성 방법의 바람직한 실시 예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.When described in detail with reference to the accompanying drawings a preferred embodiment of the metal wiring forming method according to the present invention as follows.
도 2a 내지 도 2e는 본 발명의 실시 예에 따른 금속 배선 형성 방법을 나타낸 공정 단면도이다.2A through 2E are cross-sectional views illustrating a method of forming a metal wiring according to an embodiment of the present invention.
본 발명의 실시 예에 따른 금속 배선 형성 방법은 도 2a에서와 같이, 반도체기판(31)상에 제 1 비피에스지(Boron Phosphrus Silicate Glass : BPSG)층(32), 아이피오(Inter Poly Oxide : IPO)층(33) 및 제 2 BPSG층(34)을 순차적으로 형성한다.According to an exemplary embodiment of the present invention, a metal wiring forming method according to an embodiment of the present invention may include a first BPSG layer 32 and an interpoly oxide (IPO) layer on a semiconductor substrate 31, as shown in FIG. 2A. ) Layer 33 and second BPSG layer 34 are formed sequentially.
도 2b에서와 같이, 상기 제 2 BPSG층(34)상에 감광막(35)을 도포하고, 상기 감광막(35)을 금속 배선 트렌치가 형성될 부위에서만 제거되도록 선택적으로 노광 및 현상한다.As shown in FIG. 2B, a photoresist film 35 is coated on the second BPSG layer 34, and the photoresist film 35 is selectively exposed and developed to be removed only at a portion where a metal wiring trench is to be formed.
그리고, 상기 선택적으로 노광 및 현상된 감광막(35)을 마스크로 상기 제 2 BPSG층(34)과 IPO층(33)을 선택 식각하여 금속 배선 트렌치(36)를 형성한다.Then, the second BPSG layer 34 and the IPO layer 33 are selectively etched using the selectively exposed and developed photoresist layer 35 to form a metal wiring trench 36.
도 2c에서와 같이, 상기 감광막(35) 측면에 300 ∼ 500Å 두께의 폴리머 측벽(37)을 형성한다.As shown in FIG. 2C, a polymer sidewall 37 having a thickness of 300 to 500 Å is formed on the side surface of the photosensitive film 35.
도 2d에서와 같이, 상기 감광막(35)과 폴리머 측벽(37)을 마스크로 상기 제 1 BPSG층(32)을 선택 식각하여 그 하부부위가 포지티브 슬로프의 식각 형상(B)을 갖는 금속 배선 콘택홀(38)을 형성한다.As shown in FIG. 2D, the first BPSG layer 32 is selectively etched using the photosensitive film 35 and the polymer sidewall 37 as a mask, and a lower portion thereof has a metal slope contact hole having an etched shape B of a positive slope. (38) is formed.
도 2e에서와 같이, 상기 감광막(35)과 폴리머 측벽(37)을 제거하고, 상기 금속 배선 콘택홀(38)을 포함한 전면에 베리어(Barrier)층으로 티타늄(Ti)(39)층과 TiN층(40)을 순차적으로 형성한다.As shown in FIG. 2E, the photosensitive film 35 and the polymer sidewall 37 are removed, and a titanium (Ti) layer 39 and a TiN layer are formed as a barrier layer on the entire surface including the metal wiring contact hole 38. 40 are formed sequentially.
본 발명의 금속 배선 형성 방법은 감광막 패턴을 마스크로 1차 식각된 층간 절연막을 상기 측벽에 폴리머가 발생된 감광막 패턴을 마스크로 제 2 차 식각하여 그 하부부위가 포지티브 슬로프의 식각 형상을 갖는 금속 배선 콘택홀을 형성하므로, 상기 금속 배선 콘택홀 하부부위에도 베리어층이 형성되어 금속 배선 형성층인 알루미늄층의 형성 공정 시 상기 금속 배선 콘택홀 하부부위의 보이드 발생을 방지하므로 금속 배선의 신뢰성을 향상시키는 효과가 있다.In the method of forming a metal wire according to the present invention, the interlayer insulating film firstly etched using the photoresist pattern as a mask is secondly etched using the photosensitive film pattern where polymer is generated on the sidewalls as a mask, and the lower portion thereof has an etching shape of a positive slope. Since the contact hole is formed, a barrier layer is formed on the lower portion of the metal wiring contact hole, thereby preventing voids in the lower portion of the metal wiring contact hole during the forming of the aluminum layer, which is the metal wiring forming layer, thereby improving reliability of the metal wiring. There is.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000036952A KR20020002700A (en) | 2000-06-30 | 2000-06-30 | Method for forming metal line |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000036952A KR20020002700A (en) | 2000-06-30 | 2000-06-30 | Method for forming metal line |
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|---|---|
| KR20020002700A true KR20020002700A (en) | 2002-01-10 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000036952A Withdrawn KR20020002700A (en) | 2000-06-30 | 2000-06-30 | Method for forming metal line |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103311284A (en) * | 2013-06-06 | 2013-09-18 | 苏州晶湛半导体有限公司 | Semiconductor device and production method thereof |
-
2000
- 2000-06-30 KR KR1020000036952A patent/KR20020002700A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103311284A (en) * | 2013-06-06 | 2013-09-18 | 苏州晶湛半导体有限公司 | Semiconductor device and production method thereof |
| US9640624B2 (en) | 2013-06-06 | 2017-05-02 | Enkris Semiconductor, Inc. | Semiconductor device and manufacturing method therefor |
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