KR20020009794A - Blind via hole을 갖는 다층인쇄회로기판의제조방법 - Google Patents
Blind via hole을 갖는 다층인쇄회로기판의제조방법 Download PDFInfo
- Publication number
- KR20020009794A KR20020009794A KR1020000043270A KR20000043270A KR20020009794A KR 20020009794 A KR20020009794 A KR 20020009794A KR 1020000043270 A KR1020000043270 A KR 1020000043270A KR 20000043270 A KR20000043270 A KR 20000043270A KR 20020009794 A KR20020009794 A KR 20020009794A
- Authority
- KR
- South Korea
- Prior art keywords
- printed circuit
- rcc
- stacked
- substrate
- blind via
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000011889 copper foil Substances 0.000 claims abstract description 30
- 238000000206 photolithography Methods 0.000 claims abstract description 17
- 229920005989 resin Polymers 0.000 claims abstract description 17
- 239000011347 resin Substances 0.000 claims abstract description 17
- 238000007747 plating Methods 0.000 claims abstract description 14
- 229910052802 copper Inorganic materials 0.000 claims abstract description 9
- 239000010949 copper Substances 0.000 claims abstract description 9
- 238000010030 laminating Methods 0.000 claims abstract description 6
- 238000010438 heat treatment Methods 0.000 claims abstract description 5
- 230000001678 irradiating effect Effects 0.000 claims abstract description 3
- 238000003825 pressing Methods 0.000 claims abstract description 3
- 239000010410 layer Substances 0.000 description 14
- 239000011229 interlayer Substances 0.000 description 8
- 239000004642 Polyimide Substances 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000004760 aramid Substances 0.000 description 1
- 229920003235 aromatic polyamide Polymers 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000004643 cyanate ester Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000004810 polytetrafluoroethylene Substances 0.000 description 1
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/421—Blind plated via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
Claims (2)
- 그 양측이 동박이 적층된 동박적층판(CCL)상에 통상의 사진식각공정을 통하여 제 1 인쇄회로패턴을 형성하는 단계;그 일측면에 레진이 부착된 동박(RCC)을 상기 패턴이 형성된 기판에 1차 적층시키고 이를 가압,가열하는 단계;상기 RCC가 1차 적층된 기판에 통상의 사진식각공정으로 제 2 인쇄회로패턴을 형성한 후, RCC를 2차로 적층시켜 가열,가압하는 단계;상기 RCC가 2차 적층된 기판 소정의 위치에 야그 레이저를 조사하여 2차 적층된 RCC를 제거하고, 연속하여 노출된 1차 적층된 RCC의 동박부는 통상의 사진식각공정으로 제거하고 레진부는 CO2레이저를 조사하여 제거하므로써 Blind via hole을 형성하는 단계; 및상기 Blind via hole이 형성된 기판에 무전해 및 전해동도금한 후 제 3 인쇄회로패턴을 형성하므로써 제 1-2-3 인쇄회로패턴을 전기적으로 연결하는 단계;를 포함하여 구성됨을 특징으로 하는 Blind via hole을 갖는 다층인쇄회로기판의 제조방법
- 제 1항에 있어서, 상기 2차 적층된 RCC를 제거함에 있어서, 그 동박부는 통상의 사진식각공정으로, 레진부는 CO2레이저를 조사하여 제거함을 특징으로 하는 Blind via hole을 갖는 다층인쇄회로기판 제조방법
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000043270A KR20020009794A (ko) | 2000-07-27 | 2000-07-27 | Blind via hole을 갖는 다층인쇄회로기판의제조방법 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000043270A KR20020009794A (ko) | 2000-07-27 | 2000-07-27 | Blind via hole을 갖는 다층인쇄회로기판의제조방법 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20020009794A true KR20020009794A (ko) | 2002-02-02 |
Family
ID=19680232
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000043270A Ceased KR20020009794A (ko) | 2000-07-27 | 2000-07-27 | Blind via hole을 갖는 다층인쇄회로기판의제조방법 |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20020009794A (ko) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100607626B1 (ko) * | 2004-05-25 | 2006-08-01 | 대덕전자 주식회사 | 인쇄 회로 기판에 있어서 레진 도포된 동박을 이용한 평탄코팅 공법 |
| CN112040674A (zh) * | 2020-07-07 | 2020-12-04 | 广德三生科技有限公司 | 阶梯盲槽孔混压高频微波印刷电路板及其加工方法 |
| EP4572539A1 (en) | 2023-12-11 | 2025-06-18 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Component carrier and method for manufacturing a component carrier |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1027960A (ja) * | 1996-07-09 | 1998-01-27 | Mitsui Mining & Smelting Co Ltd | 多層プリント配線板の製造方法 |
| JPH11145621A (ja) * | 1997-11-04 | 1999-05-28 | Sumitomo Metal Ind Ltd | 多層配線基板とその製造方法 |
| JPH11266084A (ja) * | 1997-12-02 | 1999-09-28 | Samsung Electro Mech Co Ltd | 多層印刷回路基板の製造方法 |
-
2000
- 2000-07-27 KR KR1020000043270A patent/KR20020009794A/ko not_active Ceased
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1027960A (ja) * | 1996-07-09 | 1998-01-27 | Mitsui Mining & Smelting Co Ltd | 多層プリント配線板の製造方法 |
| JPH11145621A (ja) * | 1997-11-04 | 1999-05-28 | Sumitomo Metal Ind Ltd | 多層配線基板とその製造方法 |
| JPH11266084A (ja) * | 1997-12-02 | 1999-09-28 | Samsung Electro Mech Co Ltd | 多層印刷回路基板の製造方法 |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100607626B1 (ko) * | 2004-05-25 | 2006-08-01 | 대덕전자 주식회사 | 인쇄 회로 기판에 있어서 레진 도포된 동박을 이용한 평탄코팅 공법 |
| CN112040674A (zh) * | 2020-07-07 | 2020-12-04 | 广德三生科技有限公司 | 阶梯盲槽孔混压高频微波印刷电路板及其加工方法 |
| EP4572539A1 (en) | 2023-12-11 | 2025-06-18 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Component carrier and method for manufacturing a component carrier |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100688743B1 (ko) | 멀티 레이어 커패시터 내장형의 인쇄회로기판의 제조방법 | |
| KR100688826B1 (ko) | 리지드-플렉시블 인쇄회로기판 제조방법 | |
| US8726495B2 (en) | Multi-layer board manufacturing method thereof | |
| US20100024212A1 (en) | Method of fabricating multilayer printed circuit board | |
| EP2001271A2 (en) | Method for making a multilayered circuitized substrate | |
| EP0483979B1 (en) | Method for producing printed circuit boards | |
| KR100222752B1 (ko) | 레이저를 이용한 다층 인쇄회로기판의 제조방법 | |
| KR100897650B1 (ko) | 다층 인쇄회로기판의 제조방법 | |
| US6080668A (en) | Sequential build-up organic chip carrier and method of manufacture | |
| KR20020009794A (ko) | Blind via hole을 갖는 다층인쇄회로기판의제조방법 | |
| US6555016B2 (en) | Method of making multilayer substrate | |
| JP2010123772A (ja) | プリント配線板の位置認識マークおよびプリント配線板の製造方法 | |
| KR100651422B1 (ko) | 일괄 적층 방식을 이용한 다층 인쇄회로기판의 제조 방법 | |
| KR100222753B1 (ko) | 절연신뢰성이 향상된 다층 인쇄회로기판의 제조방법 | |
| JP2000165039A (ja) | プリント配線板の製造方法 | |
| KR19990048049A (ko) | 빌드업 다층 인쇄회로기판의 제조방법 | |
| KR100688865B1 (ko) | 도금에 의한 범프 형성 방법 및 이를 이용한 인쇄회로기판제조방법 | |
| JP3288290B2 (ja) | 多層プリント配線板 | |
| KR100704917B1 (ko) | 인쇄회로기판 및 그 제조방법 | |
| KR19990047208A (ko) | 다층인쇄회로기판의 제조방법 | |
| KR100651342B1 (ko) | 전도성 액상 감광성 물질을 이용한 다층 인쇄회로기판의제조 방법 | |
| JP2002064273A (ja) | 多層プリント基板 | |
| GB2247113A (en) | A terminal for a multi-layer printed circuit board | |
| JPH0548246A (ja) | フレキシブルプリント配線板の製造方法 | |
| JP2001332855A (ja) | 多層配線基板の製造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 20000727 |
|
| PA0201 | Request for examination | ||
| PG1501 | Laying open of application | ||
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20020329 Patent event code: PE09021S01D |
|
| E601 | Decision to refuse application | ||
| PE0601 | Decision on rejection of patent |
Patent event date: 20020628 Comment text: Decision to Refuse Application Patent event code: PE06012S01D Patent event date: 20020329 Comment text: Notification of reason for refusal Patent event code: PE06011S01I |