KR20020039902A - Transconductance amplifier with improved linearity and low offset - Google Patents

Abstract

PURPOSE: A trans-conductance amplifier having an improved straight characteristic and low offset is provided to maintain a straight characteristic by minimizing the offset and using ICs having a simplified structure. CONSTITUTION: A trans-conductance amplifier is formed with the first current mirror(1) and the second current mirror(2). The first current mirror(1) includes the first reference transistor(Q1) and the first output transistor(Q2). The first reference transistor(Q1) has the first terminal connected with the first terminal of the first current source(l1) and the second terminal for receiving the second input voltage(Vin-). The first output transistor(Q2) has the first terminal for outputting the first output current(I01) and the second terminal connected with the first impedance element(R1). The second current mirror(2) includes the second reference transistor(Q4) and the second output transistor(Q3). The second reference transistor(Q4) has the first terminal connected with the first terminal of the first current source(l2) and the second terminal for receiving the first input voltage(Vin+). The second output transistor(Q3) has the first terminal for outputting the second current(I02) and the second terminal connected with the second impedance element(R2).

Description

TRANSCONDUCTION AMPLIFIER WITH IMPROVED LINEARITY AND LOW OFFSET}

TECHNICAL FIELD The present invention relates to integrated circuits and, more particularly, to integrated circuits having transconductance amplifiers with improved straightness and low offset.

A transconductance amplifier converts an input voltage signal into an output current signal, where the output current is proportional to its input voltage. In some applications, the offset of the transconductance amplifier needs to be as low as possible. Typically, the bias current of the transconductance amplifier must be reduced to meet the requirement of low offset. However, the reduced bias current results in weak linearity in the transconductance amplifier.

Figure 1 shows a conventional integrated circuit MAX436 that is being used to illustrate this problem. In the integrated circuit 10, the input voltage of the amplifier is represented by input voltage sources V _{in +} and V _in− . The output voltage (V _out ) of the output terminal (OUT) is connected to the transistors q ₁₀ and q _{12 which} are the collectors of the transistors. In summary, the voltage difference between the input terminals (IN + and IN-), V _{in +} -V _in- , is a pair of already in the transistor from q ₁ to q ₈ , in this example 4 k (k Ohm) resistor r ₁ . Is applied through the follower. Thus, the current through resistor r ₁ becomes (V _{in +} -V _in- ) / r ₁ . This current through r ₁ is delivered to the output terminal OUT and becomes the output current I _out by two current mirrors, transistors q ₉ , q ₁₀ and q ₁₁ , q ₁₂ .

If the voltage difference between IN + and IN- is zero, the quiescent currents of the transistors q ₁₀ and q ₁₂ are theoretically the same and cancel each other out so that the output current I _out disappears. The advantages of such a circuit are divided into two. First, the stop potentials of the input signal and the output signal can be freely selected according to the range of the supply voltage. Second, the bandwidth and stability of such a circuit is high because only local feedback is used.

However, this circuit has two disadvantages. First, there is no feedback from the output for this circuit to the input, so the input straightness is weak when compared to the circuit applying the feedback. Second, in this type of amplifier, the offset is unavoidable because of the imperfection of the components involved. The disadvantages are explained in more detail below.

The straightness of this type of circuit is hindered by variations in the inherent emitter resistance of the transistors q ₃ , q ₄ , q ₇ and q ₈ . Under the stop condition, in this example, the power supplies I ₁ to I ₄ , each 8 kHz, define the stop current. Under the condition that I ₁ = I ₂ = I ₃ = I ₄ = I, each unique emitter resistance from q ₁ to q ₈ is Vt / I, and Vt = k * T / q has a thermal Where k is Boltzmann's constant, T is the absolute temperature, and q is the magnitude of the electron charge. In this example, under stationary conditions, each intrinsic emitter resistance is:

26 μs / 8 μs = 3.25 μs.

The transconductance of transistors q ₁ , q ₂ , q ₅ and q ₆ is constant because the current through this transistor is constant by the power supply connected thereto. However, the current through transistors q ₃ , q ₄ , q ₇ and q ₈ depends on the input signal. If the circuit operates close to the breakpoint, the inverse of the mutual resistance (Rt), or transconductance, is r ₁ + Vt / Ie, in this example:

4㏀ + 3.25㏀ = 7.25㏀.

If circuit 10 operates at the limit, that is, at the emitter of transistor q ₂ and at the base of transistor q ₄ at ground, at IN − at 1 Vbe, which is about 0.7 V at room temperature, and at IN + at 2 volts, The current through r ₁ will be approximately (V _{in +} -V _in- ) / r ₁ , or 325 mA. Under these conditions, the current through transistors q ₄ and q ₇ is 325 mA while the current through transistors q ₃ and q ₈ is close to zero. The mutual resistance then becomes approximately:

r ₁ + (Vt * r1) / (V _{in +} -V _in- ), in this example:

4 ㏀ + 26 ㎷ * 4 ㏀ / 1.3 V = 4.08 ㏀.

On the other hand, if the terminal IN + is 1V and the terminal IN- is 2 volts, the current through the transistors q ₄ and q ₇ is close to zero, and the transistors q ₃ and q ₈ pass through. The currents are 325 mA each, while the mutual resistance remains as calculated above. It is obvious that the straightness is worsened by the substantial change in the mutual resistance.

Moreover, even if the input voltages at the terminals IN + and IN− are the same, there is a nearly non-zero output current Iout causing an offset. The main cause is the mismatch between the current mirrors q ₉ , q ₁₀ and q ₁₁ , q ₁₂ . This mismatch occurred on the one hand because of mismatches in the region between q ₉ , q ₁₀ and each of q ₁₁ , q ₁₂ , and on the other hand because of the initial voltages of these four transistors. Since transistors q ₁₀ and q ₁₂ each have a collector-base voltage Vbe greater than transistors q ₉ and q ₁₁ , transistors q ₁₀ and q ₁₂ have a larger collector current than transistors q ₉ and q ₁₁ . Will have Since the initial voltages of the PNP and NPN transistors are nearly different, the effect on the offset will not be compensated even if the values between transistors q ₁₀ and q ₁₂ are the same. Various conventional methods have been proposed to remedy these drawbacks. However, many components were increased and the vertical space of the signal was reduced.

Therefore, there is a tradeoff between linearity and offset in the design of transconductance amplifiers. To improve straightness, the quiescent current of the circuit should be sufficient to minimize the effects from the various inherent emitter resistors of the transistors q ₃ , q ₄ , q ₇ and q ₈ . To have a low offset, the quiescent current should be as low as possible because the collector current difference between transistors q ₁₀ and q ₁₂ caused by region mismatch or initial voltage is approximately proportional to the quiescent current.

It is an object of the present invention to provide a structure for maintaining excellent linear performance with a simplified integrated circuit of a transconductance amplifier while minimizing offset.

1 is a circuit diagram of a transconductance amplifier according to the prior art,

2 is a circuit diagram of a transconductance amplifier according to the present invention;

3 is another circuit diagram of a transconductance amplifier in accordance with the present invention.

♣ Explanation of symbols for main part of drawing ♣

1 to 5: 1st to 5th current mirror 10, 20: integrated circuit

In one embodiment, the present invention provides an integrated circuit having a differential transconductance amplifier comprising a first input voltage and a second input voltage and adapted to convert the differential input voltage into an output current. The differential transconductance amplifiers represent first and second total transconductances, respectively, during operation at stop and full drive conditions. The transconductance amplifier includes a first current mirror and a second current mirror, which are cross coupled with the first mirror.

The first current mirror has a current A and includes a first reference transistor and a first output transistor. The first reference transistor has a first terminal coupled to a second terminal adapted to accept a first current source and a second input voltage. The first output transistor has a first terminal for outputting a first output current and a second terminal connected to the first impedance element at the first node of the first impedance element. The first impedance element has a second node adapted to accept the first input voltage.

The second current mirror has a current B and includes a second reference transistor and a second output transistor. The second reference transistor has a first terminal coupled to the second current source and a second terminal adapted to receive the first input voltage. The second output transistor has a first terminal for outputting a second output current and a second terminal connected to the second impedance element at the first node of the second impedance element. The second impedance element has a second node adapted to accept a second input voltage. The output current has a difference between the first and second output currents. Preferably, the current flow A of the first current mirror is essentially the same as the current flow B of the second current mirror.

Other aspects, features and advantages of the present invention will become apparent from the following detailed description, the appended claims and the following drawings.

Circuit Description of the Invention

2 and 3, the present invention provides integrated circuits 20 and 30 each having a differential transconductance amplifier coupled to convert the differential input voltage into output current Iout. The input voltage includes a first input voltage Vin + applied to the terminal IN + and a second input voltage Vin− applied to the terminal IN−. The difference between the first and second input voltages Vin + and Vin− serves as an input voltage for the transconductance amplifier. The output current Iout can be used directly in various other types of circuits. This differential transconductance amplifier exhibits a first and a second total transconductance, respectively, during operation in a stop condition and a full drive condition.

The transconductance amplifier is composed of a first current mirror 1 and a second current mirror 2. One main feature of the present invention is that the first and second mirrors 1 and 2 are crosslinked.

The first current mirror 1 includes a first reference transistor Q1 and a first output transistor Q2. The first reference transistor Q1 has a first terminal coupled with the first terminal of the first current source I1 as shown directly in FIG. 3 or indirectly as shown in FIG. And a second terminal adapted to accept a second input voltage Vin-. The first output transistor Q2 has a first terminal for outputting the first output current I ₀₁ and a second terminal connected to the first impedance element at the first node. The first impedance element R1 has a second element adapted to accept the first input voltage Vin + as can be seen directly in FIG. 3. The first current mirror 1 has a current flow A defined by the ratio of the first output current to the current of the first current source I1 as known to those skilled in the art.

The second current mirror 2 includes a second reference transistor Q4 and a second output transistor Q3. The second reference transistor Q4 has a first terminal coupled with the first terminal of the second current source I2 and the first input voltage Vin + as shown directly in FIG. 3 and indirectly in FIG. 2. It has a second terminal adapted to receive. The second output transistor Q3 has a first terminal for outputting the second output current I02 and a second terminal connected to the second impedance element R2 at the first node. The second impedance element R2 has a second device adapted to accept the second input voltage Vin, as seen directly in FIG. 3 and indirectly in FIG. The second current mirror 2 has a current flow B defined by the ratio of the second output current to the current of the second power source I2, as is well known to those skilled in the art.

The first and second current mirrors 1 and 2 may be NPN or PNP current mirrors or N-channel or P-channel current mirrors. The current flow A of the first current mirror is essentially the same as the current flow B of the second current mirror 2.

The second terminals of the first and second current sources I1 and I2 are connected to both elements of the supply current source Vcc. First and second impedance elements R1 and R2, first and second reference transistors Q1 and Q2, first and second output transistors Q2 and Q3, and first and second power supplies I1 and I2. Are the same.

In one preferred embodiment, the first and second current mirrors 1 and 2 are two cross coupled NPN current mirrors. In more detail, the collector and base terminals of the first reference transistor Q1 are connected to the base terminal and the first current source I1 of the first output transistor Q2. Similarly, the collector and base terminal of the second reference transistor Q4 are connected to the base terminal and the second current source I2 of the second output transistor Q3. The emitter terminal of the first output transistor Q2 is connected to the first node of the first impedance element R1. The emitter terminal of the second output transistor Q3 is connected to the first node of the second impedance element R2. The second node of the first impedance element R1 is also connected to the emitter terminal of the second reference transistor Q4, and the second node of the second impedance element R2 is the emitter of the first reference transistor Q1. It is connected to the terminal. If a high impedance input is not required, the first input voltage Vin + is applied to the junction of the first impedance element R1 together with the emitter terminal of the second reference transistor Q4. The second input voltage Vin− is applied to the junction of the second impedance element R2 together with the emitter terminal of the first reference transistor Q1. The output terminals of the transconductance amplifier are the collector terminals of the first and second output transistors Q2 and Q3.

In another example, integrated circuit 20 includes a first impedance converter Q6 and a second impedance converter Q5. The first impedance converter Q6 has a high input at the first terminal receiving the first input voltage Vin + and at the second terminal connected to both the first impedance element R1 and the second terminal of the second reference transistor Q4. Provide impedance. The second impedance converter Q5 is high in the second terminal connected to both the first terminal receiving the second input voltage Vin- and the second terminal connected to both the second impedance element R2 and the first reference transistor Q1. Provide input impedance.

The first and second impedance converters Q5 and Q6 are identical. These can all be PNP or NPN emitter followers or N channel or P channel source followers. The first and second impedance converters must be in the form of opposite conductivity with the first and second current mirrors.

In another example, integrated circuit 20 includes a third current mirror 3 and a fourth current mirror 4.

The third current mirror 3 includes a third reference transistor Q7 and a third output transistor Q8. The third reference transistor Q7 has a first terminal connected to the first terminal of the first output transistor Q2 for receiving the first output current I ₀₁ . The third output transistor Q8 has a first terminal coupled to output a third output current I ₀₃ . The third current mirror 3 has a current C defined by the ratio of the third output current I ₀₃ to the first output current I ₀₁ , as is well known to those skilled in the art.

The fourth current mirror 4 includes a fourth reference transistor Q9 and a fourth output transistor Q10. The fourth reference transistor Q9 has a first terminal connected to the first terminal of the second output transistor Q3 for receiving the second output current I ₀₂ . The fourth output transistor Q10 has a first terminal for outputting the fourth output current I ₀₄ . The fourth current mirror 4 is a current flow D defined by the ratio of the fourth output current I ₀₄ to the second output current I ₀₂ , as is well known to those skilled in the art. Has)

In another preferred example, the third and fourth current mirrors 3 and 4 are PNP current mirrors. The output terminals, ie the collector terminals of the first and second output transistors Q2 and Q3 are connected to the input terminals of the third and fourth current mirrors 3 and 4, respectively. The reference potentials of the third and fourth current mirrors 3 and 4 are positive nodes of the supply current source Vcc.

In another example, integrated circuit 20 additionally has a fifth current mirror 5. The fifth current mirror 5 has a fifth reference transistor Q11 and a fifth output transistor Q12. The fifth current mirror 5 includes a fifth reference transistor Q11 and a fifth output transistor Q12. The fifth reference transistor (Q11) has a first terminal connected to the first terminal of the third output transistor (Q8) to receive the third output current (I _03). The first terminal of the fifth output transistor Q12 is connected to the first terminal of the fourth output transistor Q10 to form the output terminal OUT of the transconductance amplifier. The fifth current mirror 5 has the current flow 5 defined by the fifth output current I ₀₅ as the third output current I ₀₃ , as is well known to those skilled in the art. Preferably, the current flow C of the third current mirror 3 and the current flow E of the fifth current mirror 5 are essentially the same as the current flow D of the fourth current mirror 4.

In another preferred example, the fifth current mirror 5 is an NPN current mirror. The output terminal of the PNP current mirror 3 is connected to the input terminal of the fifth current mirror 5. The reference potential of the fifth current mirror 5 is a negative node of the supply current source Vcc. The output terminal of the current mirror 5 is connected to the output terminal of the current mirror 4. That is, the collector terminal of the fourth output transistor Q10 and the fifth output transistor Q12 are connected together to form the output terminal OUT of the transconductance amplifier. The current difference between the collector terminals of the fourth output transistor Q10 and the fifth output transistor Q12 becomes the output current Iout of the transconductance amplifier.

Each of the properties of the reference transistor Q1 and the output transistor Q2 of the first current mirror 1, the reference transistor Q4 and the output transistor Q3 of the second current mirror 2, and the characteristics of the first current source I1 Each value and each value of the second current source I2, each value of the first impedance element R1 and the second impedance element R2, has been selected so that those skilled in the art can see and understand the description of the present invention. The first total transconductance is essentially the same as the second total transconductance under full dynamic conditions.

Description of the functions of the present invention:

Referring to Fig. 2, for the sake of simplicity, when the transistors Q1 and Q4 are identical and the current mirrors 3, 4 and 5 have a consistent current, that is, the input and output currents reverse their signals. The same is assumed except for the following.

1. Stop condition:

There is no input signal under the stop condition. That is, the first and second input voltages Vin + and Vin− have the same value. If so, the collector currents of the first and second output transistors Q2 and Q3 are equal and thus the output current Iout, which is the difference between the collector currents of the fourth and fifth output transistors Q10 and Q12, is basically zero. . For slight deviations in the breakpoint, the circuit 20 operates differently. That is, if the collector current of the second output transistor Q3 increases because Vin− is less than Vin +, the collector current of the first output transistor Q2 will decrease by the same amount. The mutual resistance at the operating point is defined by the inherent dynamic emitter resistors of the first and second impedance elements R1 and R2, transistors Q2, Q3, Q5, and Q6. Each of these intrinsic emitter resistors is known as Vt / Ie, as is well known to those skilled in the art, where Vt is the thermal voltage and Ie is the emitter current of the transistor. Therefore, the inherent emitter resistance of the first output transistor Q2 is Vt / I _EQ2 and the intrinsic emitter resistance of the first emitter follower Q6 is Vt / (I _EQ2 + I2). Where I _EQ2 is the emitter current of transistor Q2. The total mutual resistance (Rt) equal to (Vin +-Vin-) / Iout is given by Equation 1 below:

[Equation 1]

Rt = 0.5 * (R1 + Vt / I _EQ2 + Vt / (I _EQ2 + I ₂ ))

2. Light Bulb Condition:

The input voltage difference, i.e., the difference between the first and second input voltages Vin + and Vin- is large, so that if the output transistor Q2 or Q3 carries almost no current, the circuit operates with a single end. Assuming that the first output transistor Q2 does not carry any current, the current through the second output current transistor Q3 is almost entirely determined by the input voltage difference and the second impedance element R2. That is, I _EQ3 is equal to (Vin + _-Vin- ) / R2, where I _EQ3 is the emitter current of transistor Q3. At this high current, the intrinsic emitter resistance is small compared to R2,

Rt ≒ R1 = R2

The specific mutual resistance Rt will usually be achieved during the design of such a circuit. Since there are no parameters to change, it is a good choice to make R1 equal to Rt.

3. Conclusion:

In order to have at least the same mutual resistance under both quiescent and full dynamic conditions, the following equation (2) must be satisfied:

[Equation 2]

0.5 * (R1 + Vt / I _EQ2 + Vt / (I _EQ2 + I ₂ )) = R1

This is satisfied when the circuit is designed under full run conditions.

[Equation 3]

Vt / I _EQ2 + Vt / (I _EQ2 + I ₂ ) = R1

If there is no need to provide a high Ohm input resistance, the first and second emitter followers Q5 and Q6 are omitted, and the above equation is reduced to the following equation:

[Equation 4]

Vt / I _EQ2 = R1

Therefore, the equation I _EQ2 = Vt / R1 must be selected.

However, if there are first and second emitter followers Q5 and Q6, there is no simple solution to determining I _EQ2 . Instead, a computer program should be used in the iteration to determine transcendental equations such as:

[Equation 5]

Where N is the area coefficient of Q2 for Q1 and Q3 for Q4, respectively.

A good starting value for repetition is to select I _EQ2 = Vt / R1.

If I choose N and determine I _EQ2 I1, I2 can be calculated for each.

Under the stop condition, the relationship between I1 and I2 and I _EQ2 , respectively I _EQ3 , is given by Equation 6:

[Equation 6]

For the value given to integrated circuit 20, I _EQ2 and I _EQ3 will be 8 dB as in integrated circuit 10. Under the conditions of all-round operation, the mutual resistance of the integrated circuit 20 is 4 kW as in the integrated circuit 10. The mutual resistance under the stop condition of the integrated circuit 20 is given by the following equation:

[Equation 7]

Rt = 0.5 * (R1 + Vt / I _EQ2 + Vt / (I _EQ2 + I ₁ )) = 0.5 * (4k Ohm + 26mV / 8㎂ +

26mV / (27.7㎂ + 8㎂)) = 4.13k Ohm

The dimensions of each of the components shown here are for illustrative purposes only and are not used to limit the scope of the invention.

Although there is a deviation with respect to the ideal mutual resistance, the deviation is much smaller than the conventional integrated circuit 10. Since the integrated circuit 20 of the present invention has less variation in mutual resistance, it has much better linearity than the conventional one.

4. Deviation from Standard Circuit

The fourth current mirror 4 of the present invention has essentially the same current flow as the third and fifth currents 3 and 5. In other words, if the fourth current mirror 4 has a current flow of D which means that the output current is D times the input current, the result of the current flow of the third and fifth current mirrors 3 and 5 is also D. Should be. By this modification, the transconductance of the voltage to the current amplifier is D / R1.

It will be fully understood that the description, material and arrangement of the parts depicted and illustrated to explain the nature of the invention have been made by those skilled in the art without departing from the spirit and scope of the invention as expressed in the following claims.

The transconductance amplifier of the integrated circuit according to the present invention described above has an improved straightness and low offset.

Claims (19)

In an integrated circuit having a differential transconductance amplifier adapted to convert a differential input voltage comprising a first input voltage and a second input voltage into an output current, the differential transconductance amplifier is respectively applied during operation in a stop condition and a full drive condition. Showing the first and second total transconductance, the transconductance amplifier: Having a first reference transistor and a first output transistor, the first reference transistor having a first terminal coupled to a second terminal adapted to receive a first current source and a second input voltage, wherein the first output transistor has a first output A first terminal for outputting current and a second terminal connected to the first impedance element at the first node of the first impedance element, the first impedance element having a second node adapted to accept the first input voltage, A first current mirror of the current flow A; And having a second reference transistor and a second output transistor cross-coupled to the first current mirror and having a current B, the second reference transistor receiving a first terminal and a first input voltage coupled to the second current source. Having a second terminal applied, the second output transistor having a first terminal for outputting a second output current and a second terminal connected to a second impedance element at a first node of the second impedance element, the second impedance element being And a second current mirror having a second node adapted to accept a second input voltage, wherein the output current comprises a second current mirror in which a difference exists between the first and second output currents. The method of claim 1, And the current flow A of the first current mirror is essentially the same as the current flow B of the second current mirror. The method of claim 1, And further comprising a first impedance converter and a second impedance converter, wherein the first impedance converter includes both the first terminal and the second terminal of the first reference element and the second terminal of the first impedance element which receive the first input voltage. Provide a high input impedance at a second terminal connected; The second impedance converter provides a high input impedance at a second terminal connected to both the first terminal and the second terminal of the first reference transistor and the second terminal of the second impedance element to receive the second input voltage. The method of claim 1, A third reference transistor and a third output transistor, the third reference transistor having a first terminal connected to a first terminal of the first output transistor for receiving a first output current, the third output transistor being a third A third current mirror of the current flow C having a first terminal adapted for outputting an output current, and a fourth reference transistor and a fourth output transistor, wherein the fourth reference transistor is adapted to receive the second output current. A first current mirror having a first terminal connected to the first terminal of the second output transistor, the fourth output transistor further comprising a fourth current mirror of the current flow D having a first terminal adapted for outputting a fourth output current; Integrated circuits. The method of claim 4, wherein A fifth reference transistor and a fifth output transistor, the fifth reference transistor having a first terminal connected to a first terminal of a third output transistor for receiving a third output current, and the fifth output transistor having a fifth output transistor; A fifth terminal of the current transformer E having a first terminal for outputting an output current, the first terminal of the fifth output transistor being connected to the first terminal of the fourth output transistor to form an output terminal of the transconductance amplifier; An integrated circuit further comprising a current mirror. The method of claim 5, The current flow C of the third current mirror and the current flow E of the fifth current mirror are essentially the same as the current flow D of the fourth current mirror. The method of claim 1, Characteristics of the reference transistor and the output transistor of the first current mirror, the respective characteristics of the reference transistor and the output transistor of the second current mirror, respective values of the first current source and the second current source, respectively of the first impedance element and the second impedance element. Value is selected such that the first total transconductance is essentially equal to the second total transconductance. The method of claim 1, And the first and second reference transistors and the first and second output transistors are N-type semiconductors. The method of claim 1, And the first and second reference transistors and the first and second output transistors are p-type semiconductors. The method of claim 3, wherein The first and second impedance converters are made of a P-type semiconductor. The method of claim 3, wherein The first and second impedance converters are made of an N-type semiconductor. The method of claim 4, wherein And the third and fourth current mirrors are made of a P-type semiconductor. The method of claim 4, wherein And the third and fourth current mirrors are made of an N-type semiconductor. The method of claim 5, The fifth current mirror is made of an N-type semiconductor. The method of claim 5, The fifth current mirror is made of a P-type semiconductor. The method of claim 9, 10, 12 or 15, P-type semiconductors are bipolar PNP semiconductors. The method of claim 9, 10, 12 or 15, A P-type semiconductor is an integrated circuit which is a P-channel MOS transistor. The method of claim 8, 11, 13 or 14, An N-type semiconductor is an integrated bipolar NPN transistor. 15. The integrated circuit of claim 8, 11, 13 or 14, wherein the N-type semiconductor is a MOS N-channel transistor.