KR20020092012A - Compensating metod for time delay of digital linearization apparatus - Google Patents

Abstract

The present invention relates to a technique for calculating time delays more accurately without using a separate delay line in a digital linearizer. The present invention is a signal directly input to the predistorter from the input stage ( ) And the signal input back from the directional coupler through the main path ( A first step of collecting) for a predetermined time and interpolating; Obtaining a magnitude of the two interpolated signals, obtaining an average ratio of these values, and multiplying the two signals by a feedback input signal; The k value, which is the divisor constant value of the oversampling rate, is changed and the time difference between the two signals with the corresponding magnitudes is repeated each time. When the time difference becomes the minimum, it is determined that the time delay between them is the minimum. signal( ), ( Is achieved by a third process giving an offset equal to that K value between the < RTI ID = 0.0 >

Description

Compensation for Time Delay in Digital Linearizers {COMPENSATING METOD FOR TIME DELAY OF DIGITAL LINEARIZATION APPARATUS}

The present invention relates to a technique for compensating a time delay between a reference signal and an error signal fed back in a digital linearizer, and in particular, a time delay of a digital linearizer to more accurately compensate for a time delay without using a separate delay line. It is about a compensation method.

FIG. 1 is a block diagram of a digital linearizer according to the prior art. As shown in FIG. 1, a digital signal I / Q input through an input terminal 100 is modulated and an error component input from an error detector 111 is used. A digital modulation and predistorter (101) for compensating for the nonlinear characteristics; A D / A converter (102) for converting a digital signal output from the digital modulation and predistorter (101) into an analog signal; A low pass filter 103 for low pass filtering the output signal of the D / A converter 102; An up converter (104) for converting an output signal of the low pass filter (103) to a frequency of a specific band by using an output signal of a local oscillator (107); A main amplifier 105 for amplifying the output signal of the up-converter 104 to a predetermined level; A directional coupler (106) for branching the trunk signal without changing the impedance of the output signal of the main amplifier (105); A down converter (108) for converting the signal branched from the directional coupler (106) to the frequency of the original band by using the output signal of the local oscillator (107); An A / D converter (109) for converting an analog signal output from the down converter (108) into a digital signal; An error detector for detecting an error component generated in the main amplifier 105 by comparing a signal fed back through the A / D converter 109 and a signal directly input from the input terminal 100 through the delay unit 110 ( 111), its operation is as follows.

After the digital signal I / Q input through the input terminal 100 is modulated by the digital modulation and predistorter 101 configured as shown in FIG. 2, the non-linear characteristic according to the error component input from the error detector 111 is obtained. This is compensated for.

The digital signal output from the digital modulator and predistorter 101 is converted into an analog signal through the D / A converter 102, and again filtered through the low pass filter 103, and then filtered by the up converter 104. Converted to the frequency of the band.

In addition, the output signal of the up-converter 104 is amplified to a predetermined level by the main amplifier 105, and then the trunk signal is separated by the directional coupler 106 to be output to the output terminal (Output).

Meanwhile, the error detector 111 detects an error component on the main path from the digital modulation and predistorter 101 to the directional coupler 106, and inputs not through the main path and the signal input through the feedback path. Compare the signals to detect the error components.

That is, the down converter 108 converts the frequency of the signal returned from the directional coupler 106 to the frequency of the original band by using the output signal of the local oscillator 107, and the analog signal thus converted is A /. The D converter 109 converts the digital signal. At this time, the error detector 111 is generated in the main amplifier 105 by comparing the signal fed back through the A / D converter 109 and the signal directly input from the input terminal 100 through the delay unit 110 The error component to be detected is detected.

As described above, the error detector 111 outputs the original signal by delaying the original signal for a predetermined time through the delay unit 110 so as to simultaneously compare the distorted signal with the original signal which is not distorted. It is implemented using a line (Microstrip Line).

On the other hand, Figure 3 shows an example of the case of employing an analog modulator for the digital modulation and predistorter in the conventional digital linearizer.

As described above, in the conventional digital linearizer, the original signal is delayed and output through a coaxial line or a microstrip line so that the distorted signal and the original signal that are not distorted can be compared at the same time. There was a falling flaw.

Accordingly, an object of the present invention is to compensate for time delay of a digital linearizer using a microprocessor or a digital signal processor used in an error detector without using a separate delay element such as a coaxial line or a microstrip line. In providing.

1 is a block diagram of a digital linearizer according to the prior art.

2 is a detailed block diagram of a digital modulator and predistorter in FIG.

3 is a block diagram of another digital linearizer following the prior art.

4 is a block diagram of a digital linearizer according to the present invention.

FIG. 5 is a detailed block diagram of a time delay compensation unit in FIG. 4. FIG.

6 is a waveform diagram of a sine wave showing a time delay compensation principle according to the present invention;

Fig. 7A is a waveform diagram of an input signal before interpolation.

7B is a waveform diagram of an input signal after interpolation.

8 (a)-(c) are waveform diagrams showing a phase change between two signals according to an increase in k value.

*** Description of the symbols for the main parts of the drawings ***

400: input stage 401: predistorter

402: D / A converter 403: low pass filter

404: IQ modulator 405: main amplifier

406: directional coupler 407: local oscillator

408: down converter 409: A / D converter

410: error detector 410A: time delay compensation unit

501A, 501B: Interpolation unit 502A, 502B: Size detection unit

503: size ratio calculator 504: multiplier

505: subtractor 506: difference value adding unit

The time delay compensation method of the digital linearizer according to the present invention includes a signal directly input to the predistorter from the input stage. ), And the signal input back from the directional coupler through the main path ( A first step of collecting) for a predetermined time and interpolating; Obtaining a magnitude of the two interpolated signals, obtaining an average ratio of these values, and multiplying the two signals by a feedback input signal; The k value, which is the divisor constant value of the oversampling rate, is changed and the time difference between the two signals with the corresponding magnitudes is repeated each time. When the time difference becomes the minimum, it is determined that the time delay between them is the minimum. signal( ), ( ), A third step of giving an offset by the value of K between the < RTI ID = 0.0 >

4 is a block diagram of a digital linearizer to which the time delay compensation method of the present invention is applied. As shown in FIG. 4, the digital signal I / Q input through the input terminal 400 is modulated, and the error detector 411 is used. A predistorter 401 for compensating for the nonlinear characteristic according to the error component input from the signal generator; A D / A converter 402 for converting the digital signal output from the predistorter 401 into an analog signal; A low pass filter 403 for low pass filtering the output signal of the D / A converter 402; An IQ modulator 404 for modulating the output signal of the low pass filter 403 using the output signal of the local oscillator 407 and outputting at a frequency of a specific band; A main amplifier (405) for amplifying the output signal of the IQ modulator (404) (404) to a predetermined level; A directional coupler 406 for branching the trunk signal to the output signal of the main amplifier 405 without a change in impedance; A down converter 408 for converting a signal branched from the directional coupler 406 and returned to the frequency of the original band using the output signal of the local oscillator 407; An A / D converter 409 for converting an analog signal output from the down converter 408 into a digital signal; A signal directly input to the predistorter 401 ) And the signal input back from the directional coupler 406 through the main path ( ) And an error detector 410 which matches the time difference by changing the k value, which is the divisor constant value of the oversampling rate, after interpolating and matching their magnitudes, respectively. A detailed description with reference to FIG. 8 is as follows.

4 is the same as in FIG. 3, except that compensation for time delay is performed using a microprocessor or a digital signal processor used in the error detector 410 without using a separate delay element.

That is, after the digital signal I / Q input through the input terminal 400 is modulated by the predistorter 401 and the nonlinear characteristic is compensated according to the error component input from the error detector 411. The D / A converter 402 converts the signal into an analog signal. The D / A converter 402 then performs low pass filtering through the low pass filter 403 and then modulates the frequency of a specific band by the IQ modulator 404. The modulated signal is amplified by the main amplifier 405 to a predetermined level, and the directional coupler 406 separates the interference signal without changing the impedance and outputs it to the output terminal.

On the other hand, the down converter 408 converts the frequency of the signal returned from the directional coupler 406 to the frequency of the original band by using the output signal of the local oscillator 407, and the analog signal thus converted is A / It is converted into a digital signal by the D converter 409. The error detector 410 receives a signal fed back through the A / D converter 409 ( And a signal directly input from the input terminal 400 ) To compensate for the time delay.

The time delay compensator 410A in the error detector 410 includes the two signals ( ), ( Assuming that) is the same signal and only time delay, we compensate for time delay by using the principle that if the difference between them becomes "0", the two signals will be the same signal without time delay. 6 shows the two signals ( ), ( ) Shows the principle of time delay compensation in case of sine wave. However, in practice, the feedback signal ( ) Contains several error components, so the two signals ( ), ( When the difference is minimum, it is judged that time delay compensation has been achieved. In fact, the time delay compensation unit 410A may be implemented using a microprocessor or a digital signal processor (DSP) built in the error detector 410. A detailed description will be given with reference to FIG. 5, which illustrates a time delay compensation process.

The time delay compensation unit 410A receives a signal directly input from the input terminal 400. ) And feedback input signal ( ) Is collected for a predetermined time, and the collected signal is expressed by the following equation.

Among the input signals collected as described above, the input signal ( ) And feedback input signal ( ) Is interpolated at an arbitrary oversampling rate (OSR) by the interpolators 501A and 501B, respectively. FIGS. 7A and 7B show waveforms representing input signals before and after interpolation. It is also.

The larger the oversampling ratio, the higher the accuracy of time delay compensation, while the longer the processing time for time delay compensation in a microprocessor or DSP.

As a preprocessing process for compensating for time delay, the two signals interpolated as described above ( ), ( ) Needs to be the same size. To this end, the two signals (using the magnitude detectors 502A and 502B) are used. ), ( ), And the size ratio calculator 503 divides the average of the magnitude values obtained by the magnitude detector 502A by the average value of the magnitude values obtained by the magnitude detector 502B. ), ( Find the ratio of magnitude to). The multiplier 504 multiplies the signal interpolated by the interpolation unit 501B with the size ratio obtained by the size ratio calculating unit 503.

After matching the magnitudes of the two signals through the above process, the signals input from the interpolator 501A and the multiplier 504 using the subtractor 505 ( ), ( The difference in time (phase difference) is calculated, and the difference value adding unit 506 obtains the sum of the difference values obtained by the subtractor 505.

If the two signals ( ), ( In an ideal case where) is the same and there is no time difference between them, the output value of the difference value adder 506 will be "0". However, when there is a time delay as shown in FIG. 6, the output value does not become zero and has a value corresponding to the delay time.

In order to compensate for the time delay, if the difference value adding unit 506 increases the value k of the divisor constant of the oversampling rate by 1 and repeats the above-described operation of calculating the sum of the difference values, the output thereof becomes as follows. .

(A), (b), and (c) of FIG. 8 illustrate the two signals as the value of k increases. ), ( Is a waveform diagram showing that the relationship of) changes sequentially. In other words, two signals ( ), ( For example, the sum of the differences with respect to) gradually decreases.

As a result, when the output value of the difference value adding unit 506 is changed by changing the k value, the two signals ( ), ( The time delay of) is minimized.

Therefore, two signals ( ), ( Offsets between the two signals can be used in ideal cases without time delay ), ( ) Can be compared, and the time delay value is expressed by the following equation.

As described in detail above, the present invention enables the compensation of the time delay by using a microprocessor or a digital signal processor which is already used without using a separate delay element such as a coaxial line or a microstrip line. This reduces the cost and improves signal reproducibility.

Claims (4)

Signal directly input to the predistorter from the input stage ( ) And the signal input back from the directional coupler through the main path ( Interpolating the first step; A second step of acquiring the magnitudes of the two interpolated signals, acquiring the average ratio thereof, and multiplying them by a feedback input signal; And a third step of varying the value of k, which is a divisor constant for the oversampling rate, and then repetitively calculating the time difference between the two signals having the same magnitude, and obtaining the value of k that minimizes the time difference. Time Delay Compensation Method of Digital Linearizer. The method of claim 1, wherein the second process uses two magnitudes to detect two signals. ), ( A first step of obtaining the size of n); The signal ( Signal is the average of the magnitude values Dividing by the average of the magnitude values) to obtain a ratio of the magnitudes between them; And a third step of multiplying the magnitude ratio by a signal that is interpolated and fed back. The method of claim 1, wherein the third process includes two signals (offset) corresponding to the K value that minimizes the time difference. ), ( The time delay compensation method of the digital linearizer characterized in that it further comprises the step of). 2. The method of claim 1, wherein k and the time delay value have a relationship as in the following equation.