KR940016902A - 모스(mos) 트랜지스터 제조방법 - Google Patents

모스(mos) 트랜지스터 제조방법 Download PDF

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Publication number
KR940016902A
KR940016902A KR1019920024909A KR920024909A KR940016902A KR 940016902 A KR940016902 A KR 940016902A KR 1019920024909 A KR1019920024909 A KR 1019920024909A KR 920024909 A KR920024909 A KR 920024909A KR 940016902 A KR940016902 A KR 940016902A
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KR
South Korea
Prior art keywords
forming
substrate
impurity layer
gate
oxide film
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KR1019920024909A
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English (en)
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KR950013792B1 (ko
Inventor
신형순
김영관
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문정환
금성일렉트론 주식회사
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Priority to KR1019920024909A priority Critical patent/KR950013792B1/ko
Publication of KR940016902A publication Critical patent/KR940016902A/ko
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 자기 정열된 얇은 P--LDD(Lightly Doped Drain) 접합형성에 적합하도록 한 모스 트랜지스터 제조방법에 관한 것으로 저농도 불순물층(4)을 얇게접합시켜 쇼트 채널효과를 줄일수 있는 MOS 트랜지스터 제조방법을 제공함에 그 목적이 있다.
본 발명은 상기 목적을 달성하기 위하여 기판(1)상에 절연막(2)을 형성하고 폴리실리콘(3)과 산화막(4)을 증착하여 패턴링함으로써 게이트전극을 형성하는 제 1 공정, 상기 게이트(3) 측벽과 기판(1)상에 산화막을 형성하고 불순물을 증착, 상기 게이트(3) 측벽에만 남도록 식각함으로써 게이트 측벽 불순물층(8)을 형성하는 제 2 공정, 상기 산화막(7)을 통해 보론을 기판(1)에 확산시켜 저농도 불순물층(9)을 형성하는 이온주입으로 고농도 불순물층(6)을 형성하는 제 3 공정으로 이루어짐을 특징으로 한다.

Description

모스(MOS) 트랜지스터 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 2 도는 본 발명의 일실시예를 나타내는 공정순서도.

Claims (2)

  1. 기판(1)상에 절연막(2)을 형성하고 폴리실리콘(3)과 산화막(4)을 증착하여 패턴링함으로써 게이트 전극을 형성하는 제 1 공정, 상기 게이트(3) 측벽과 기판(1)상에 산화막(8)을 형성하고 불순물을 증착, 상기 게이트(3) 측벽에만 남도록 식각하여 게이트측벽 불순물층(9)을 형성하는 제 2 공정, 상기 산화막(8)을 통해 보론을 기판(1)에 확산시켜 저농도 불순물층(10)을 형성한후 이온주입으로 고농도 불순물층(7)을 형성하는 제 3 공정으로 이루어짐을 특징으로 하는 모스 트랜지스터 제조방법.
  2. 제 1 항에 있어서, 상기 제 3 공정중 보론 확산 방법은 RTP(Rapid Thermal Process)법을 이용함을 특징으로 하는 모스 트랜지스터 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920024909A 1992-12-21 1992-12-21 모스(mos) 트랜지스터 제조방법 Expired - Lifetime KR950013792B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920024909A KR950013792B1 (ko) 1992-12-21 1992-12-21 모스(mos) 트랜지스터 제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920024909A KR950013792B1 (ko) 1992-12-21 1992-12-21 모스(mos) 트랜지스터 제조방법

Publications (2)

Publication Number Publication Date
KR940016902A true KR940016902A (ko) 1994-07-25
KR950013792B1 KR950013792B1 (ko) 1995-11-16

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Application Number Title Priority Date Filing Date
KR1019920024909A Expired - Lifetime KR950013792B1 (ko) 1992-12-21 1992-12-21 모스(mos) 트랜지스터 제조방법

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KR (1) KR950013792B1 (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100965213B1 (ko) * 2002-12-30 2010-06-22 동부일렉트로닉스 주식회사 반도체 장치의 트렌지스터 형성 방법

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