KR950000278B1 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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KR950000278B1
KR950000278B1 KR1019910023895A KR910023895A KR950000278B1 KR 950000278 B1 KR950000278 B1 KR 950000278B1 KR 1019910023895 A KR1019910023895 A KR 1019910023895A KR 910023895 A KR910023895 A KR 910023895A KR 950000278 B1 KR950000278 B1 KR 950000278B1
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semiconductor device
semiconductor
inner lead
semiconductor chip
leads
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KR930015036A (en
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권홍규
송병석
전기영
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삼성전자 주식회사
김광호
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/811—Multiple chips on leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

내용 없음.No content.

Description

반도체 장치 및 그 제조방법Semiconductor device and manufacturing method thereof

제 1 도는 칩 패드(chip pad)의 배열과 지지대(support bar) 및 내부 리이드(inner lead)의 구조를 나타낸 도면.1 is a diagram showing an arrangement of chip pads and a structure of a support bar and an inner lead.

제 2 도는 최초의 지지대까지 내부 리이드를 삭각한 것을 나타낸 도면.2 shows the cutting of the inner lead up to the first support.

제 3 도는 리이드 프레임(Lead Frame) 뒷면에 폴리이미드(Polymide) 테이프를 붙이고 지지대와 내부 리이드 팁(tip) 사이를 없앤 것을 나타낸 도면.3 shows a polyimide tape attached to the back of a lead frame and a gap between the support and the inner lead tip.

제 4 도는 칩이 직사각형일 때의 리이드 프레임의 구조를 나타낸 도면.4 is a diagram showing the structure of a lead frame when the chip is rectangular.

본 발명은 반도체 장치 및 그 제조방법에 관한 것으로서, 특히 리이드 프레임 설계 및 그 제조방법에 관한 것이다.TECHNICAL FIELD The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a lead frame design and a method for manufacturing the same.

종래에 LOC(Lead on chip) 구조의 리이드 프레임은 메모리 제품에만 사용되었는데 사용할 수 있는 리이드 프레임의 내부 리이드의 수가 적어서 디램 분야에만 사용되었다. 앞으로의 팩키지(package)는 혼성(hybrid)화, 고집적, 고밀도로 실장화 되어가는 추세이다. 특히 디램 분야에서는 고집적화에 따른 FAB(Fabrication) 제조 공정상의 한계 때문에 멀티(multi) 칩으로 집적도를 향상시키는 방법이 연구되어 왔다. 비메모리쪽에서도 하나의 팩키지를 제조함으로써 여러개의 칩을 실장하는 효과를 낼 수 있는 팩키지 제조기술이 연구되고 있다. 이러한 종래기술의 특허로는 한국 공개 특허 번호 90-5588호에 실려 있다.In the related art, lead frames having a lead on chip (LOC) structure have been used only in memory products, and have only a small number of internal leads in lead frames. In the future, the package is being hybridized, highly integrated, and high density. In particular, in the field of DRAM, a method of improving the integration density with multi-chips has been studied due to limitations in fabrication (FAB) manufacturing process due to high integration. In the non-memory side, the manufacture of a package that can produce the effect of mounting multiple chips by manufacturing a single package is being studied. Such a prior art patent is disclosed in Korean Patent Publication No. 90-5588.

본 발명의 목적은 각각 다른 기능을 갖는 4개의 칩을 한번에 설계하여 FAB 공정을 진행한 다음 4개의 각각 다른 칩을 하나의 칩으로 잘라서 팩키지 하는 것과 아울러 4개의 각각 다른 칩을 하나의 리이드 프레임에 접착하여 어셈블리(Assembly)할 수 있는 반도체 장치 및 그 제조방법을 제공한다.An object of the present invention is to design four chips each having a different function at a time, and then go through the FAB process and then cut and package four different chips into one chip, and attach four different chips to one lead frame. The present invention provides a semiconductor device capable of assembly and a method of manufacturing the same.

본 발명의 또 다른 목적은 다(多)핀의 내부 리이드를 갖는 리이드 프레임을 제조함으로써 종래기술의 문제점을 해결할 수 잇는 반도체 장치 및 그 제조방법을 제공한다.Another object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which can solve the problems of the prior art by manufacturing a lead frame having a multi-pin internal lead.

상기한 바와 같은 본 발명의 목적을 달성하기 위하여, 본 발명은 주변에 회로와 외부단자가 형성된 사각형상의 반도체 칩, 절연체로 접착된 내부 리이드와 외부 리이드가 윗쪽에 탑재된 반도체 칩의 배열형태에 따라 사각형으로 되는 여러개의 리이드, 반도체 칩과 리이드를 전기적으로 접속하기 위한 금속 와이어, 반도체칩, 절연체, 내부 리이드·금속와이어를 봉하여 막기 위한 봉지재로 이루어지는 반도체 장치에 있어서, 상기 외부단자는 반도체 칩의 네 변에 배치되고, 또한 반도체 칩의 길이방향 및 폭방향의 중앙부위에 길이 방향 및 폭방향으로 본딩패드를 형성하는 것을 특징으로 하는 반도체 장치를 제공한다.In order to achieve the object of the present invention as described above, the present invention is a rectangular semiconductor chip formed with a circuit and an external terminal in the periphery, according to the arrangement form of the semiconductor chip mounted on the inner lead and the outer lead bonded to the upper A semiconductor device comprising a plurality of rectangular leads, a metal wire for electrically connecting the semiconductor chip and the lead, a semiconductor chip, an insulator, and an encapsulant for sealing and blocking the inner lead and the metal wire, wherein the external terminal is a semiconductor chip. The semiconductor device is disposed on four sides of the semiconductor chip, and a bonding pad is formed in the longitudinal direction and the width direction at a central portion of the semiconductor chip in the longitudinal direction and the width direction.

또한 본 발명은 내부 리이드의 형태가 반도체 칩 배열에 따라 십자형으로 배열되는 것을 특징으로 하는 반도체 장치를 제공한다.In addition, the present invention provides a semiconductor device characterized in that the shape of the inner lead is arranged crosswise in accordance with the semiconductor chip arrangement.

또한 본 발명은 내부 리이드의 변형 및 본딩성을 향상하기 위하여 4개 이상의 지지대를 갖는 것을 특징으로 하는 반도체 장치를 제공한다.In addition, the present invention provides a semiconductor device characterized by having four or more supports to improve the deformation and bonding of the inner lead.

또한 본 발명은 주변에 회로와 외부단자가 형성된 사각형상의 반도체 칩, 절연체로 접착된 내부 리이드와 외부 리이드가 윗쪽에 탑재된 반도체 칩의 배열형태에 따라 사각형으로 되는 여러개의 리이드, 반도체 칩과 리이드를 전기적으로 접속하기 위한 금속 와이어, 상기 반도체 칩과 절연체를 접속하기 위한 제1의 접착층, 상기 절연체와 내부 리이드를 접속하기 위한 제2의 접착층, 상기 반도체칩, 제1 및 제2의 접착층·절연체·내부 리이드·금속 와이어를 봉하여 막기 위한 봉지재로 되는 반도체 장치에 있어서, 상기 외부단자는 네 변에 배치되고, 내부 리이드의 앞끝은 반도체 칩 중앙부위까지 근접하여 배치되는 것을 특징으로 하는 반도체 장치를 제공한다.In addition, the present invention is a rectangular semiconductor chip formed with a circuit and an external terminal in the periphery, a plurality of leads, semiconductor chips and leads that are rectangular in accordance with the arrangement of the semiconductor chip mounted on the inner lead and the outer lead attached to the upper A metal wire for electrically connecting, a first adhesive layer for connecting the semiconductor chip and the insulator, a second adhesive layer for connecting the insulator and the inner lead, the semiconductor chip, the first and second adhesive layers and insulators; A semiconductor device comprising an encapsulant for sealing and blocking an inner lead and a metal wire, wherein the outer terminal is disposed on four sides, and the front end of the inner lead is disposed close to the center of the semiconductor chip. to provide.

또한 본 발명은 처음에 지지대까지 내부 리이드를 식각하고 내부 리이드 본딩 부위에 온(Ag) 플레이팅(plating)을 실시한 후, 리이드 프레임 뒷면에 테이프를 부착하고 지지대와 내부 리이드 본딩 부분을 스탬핑(stamping) 또는 식각하여 자르는 것을 특징으로 하는 반도체 장치의 제조방법을 제공한다.In addition, the present invention first etching the inner lead to the support and after the (Ag) plating on the inner lead bonding portion, attaching a tape to the back of the lead frame and stamping the support and the inner lead bonding portion (stamping) Or it provides a method of manufacturing a semiconductor device characterized in that the etching to cut.

이하 본 발명의 바람직한 실시예를 첨부한 도면에 따라 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

제 1 도는 칩 패드(1)의 배열과 지지대92) 및 내부 리이드(3)의 구조를 나타낸 도면으로서, 외부 리이드(도시되지 않았음)가 내부 리이드(3)로 꺽어지는 부분은 칩의 외곽선(4)을 기준으로 하고 칩 패드 중심의 위치는 내부 리이드의 중앙선(5)에 일치하게 배열된다. 여기서 F는 하나의 디아빙스 특성을 갖는 칩의 한변의 길이를 나타내고 G는 칩 패드 중심에 내부 리이드가 접속된 부분을 나타낸다.1 is a view showing the arrangement of the chip pad 1 and the structure of the support 92 and the inner lead 3, wherein the portion where the outer lead (not shown) is bent by the inner lead 3 is the outline of the chip ( The position of the chip pad center with respect to 4) is arranged to coincide with the center line 5 of the inner lead. F denotes the length of one side of the chip having one diavings characteristic, and G denotes a portion where the inner lead is connected to the center of the chip pad.

제 2a 도는 최초의 지지대(2)까지 내부 리이드(3)를 식각한 것을 나타낸 도면으로서, 내부 리이드(3)와 칩패드(1) 사이의 간격은 와이어 본딩에 이상이 없을 정도로 최대한 줄인다. 제 2b 도는 리이드 프레임 뒷면에 접착테이프(6)를 붙인 것을 나타낸 도면이다. 여기서 A는 내부 리이드(3) 사이의 피치(pitch)를 나타내고 B는 칩 패드(1) 사이의 피치를 나타낸다.FIG. 2A shows the etching of the inner lead 3 to the first support 2, whereby the spacing between the inner lead 3 and the chip pad 1 is reduced as much as possible so that there is no abnormality in the wire bonding. 2b is a view showing the adhesive tape 6 attached to the back of the lead frame. Where A represents the pitch between the inner leads 3 and B represents the pitch between the chip pads 1.

한편, C는 칩 패드 패턴의 단위로서 스크라이브 중심선(7)과 칩 패드(1) 사이의간격을 나타내과, D는 접착 테이프(6)과 칩 패드(1) 사이의 간격을 나타내며, E는 C와 같은 간격을 나타낸다.On the other hand, C denotes the distance between the scribe center line 7 and the chip pad 1 as a unit of the chip pad pattern, D denotes the distance between the adhesive tape 6 and the chip pad 1, and E represents Show the same spacing.

제 3 도는 리이드 프레임 뒷면에 폴리이미드 테이프(6)를 붙이고 지지대92)와 내부 리이드 팁 사이을 없앤 것을 나타낸 도면으로, 여기서 내부 리이드(3)는 뒤틀림(bent)을 방지하고 다이(die) 접착을 위하여 열압착 본딩용 폴리이미드 테이프를 붙인다.3 is a view showing the polyimide tape 6 attached to the rear of the lead frame and the gap between the support 92 and the inner lead tip, wherein the inner lead 3 is prevented from bending and die-bonded. Apply polyimide tape for thermocompression bonding.

제 4 도는 칩이 직사각형일 때의 리이드 프레임 구조를 나타낸 도면으로 직사각형 형태의 칩을 접착할 때는 꺽어지는 기준선(8)을 짧은 변의 길이로 한다.4 is a view showing a lead frame structure when the chip is rectangular. When the chip of the rectangular shape is bonded, the reference line 8, which is bent, is set to have a short side length.

리이드 프레임 제조공정이 끝나면 팩키지를 하게 되는데, 우선 접착 플레이트에 리이드 프레임을 얼라인(align)한 뒤, 본딩 플레이트 위에 칩을 로딩하고 나서 플레이트를 리이드 프레임 밑으로 이동하여 정확하게 얼라인한다. 그 다음 열압착 방식으로 칩을 리이드 프레임에 접착하고 와이어 본딩을 한 후, 몰딩(molding)을 하고 어셈블리 공정을 진행시킨다.After the lead frame manufacturing process is completed, the package is prepared. First, the lead frame is aligned on the adhesive plate, the chip is loaded on the bonding plate, and then the plate is moved under the lead frame to align accurately. Then, the chips are bonded to the lead frame by thermocompression bonding and wire bonding, followed by molding and the assembly process.

그런데, 기존 멀티 칩방식으로는 팩키지의 크기가 커지는 문제점이 발생한다. 본 발명은 기존 리이드 프레임으로 제조할 때 문제가 되는 와이어 본딩 루프(loop) 길이로 인한 팩키지 크기가 커지는 문제와 기존 리이드 프레임 같이 칩 패드를 칩의 외곽에 배치함으로써 생기는 칩 크기 극대화 및 디바이스(device) 작동시 속도저하 문제를 해결할 수 있다. 장비도 기존의 장비를 이용하여 제조할 수 있으며, 고집적, 고기능, 고밀도 실장을 가능하게 하는 효과가 있으며, 그 결과 팩키지를 실장하는 PCB(Print Circuit Poard)나 세트(set) 등의 크기나 부피를 줄일 수 있는 효과가 있다.However, there is a problem that the size of the package increases with the existing multi-chip method. According to the present invention, the size of the package is increased due to the length of the wire bonding loop, which is a problem when manufacturing the conventional lead frame, and the chip size maximization and device caused by placing the chip pad on the outside of the chip, such as the existing lead frame. It can solve the problem of slowing down during operation. The equipment can also be manufactured using existing equipment, and has the effect of enabling high integration, high performance, and high density mounting. As a result, the size or volume of a printed circuit board (PCB) or a set for mounting a package can be increased. There is an effect that can be reduced.

또한, QEP(Quad Flat Package) 등에 적용하면 600핀 이상의 하이 핀(high pin) 팩키지 제조도 가능하다.In addition, when applied to a QEP (Quad Flat Package), it is possible to manufacture a high pin package of 600 pins or more.

Claims (7)

주변에 회로와 외부 단자가 형성된 사각형상의 반도체 칩, 절연체로 접착된 내부 리이드와 외부 리이드가 윗쪽에 탑재된 반도체 칩의 배열 형태에 따라 사각형으로 되는 여러개의 리이드, 반도체 칩과 리이드를 전기적으로 접속하기 위한 금속 와이어, 반도체칩·절연체·내부리이드·금속와이어를 봉하여 막기 위한 봉지재로 이루어지는 반도체 장치에 있어서, 상기 외부 단자는 반도체 칩의 네 변에 배치되고, 또한 반도체 칩의 길이방향 및 폭방향의 중앙부위에 길이 방향 및 폭방향으로 본딩패드를 형성하는 것을 특징으로 하는 반도체 장치.Electrically connecting the semiconductor chips and the leads, which are rectangular in shape according to the arrangement of the semiconductor chip having the circuit and the external terminal formed in the periphery, the inner lead bonded by the insulator, and the semiconductor chip mounted on the upper lead. A semiconductor device comprising a metal wire, a semiconductor chip, an insulator, an inner lead, and an encapsulant for sealing and blocking a metal wire, wherein the external terminal is disposed on four sides of the semiconductor chip, and the semiconductor chip is in a longitudinal direction and a width direction thereof. A bonding pad is formed in the longitudinal direction and the width direction in the center part of the semiconductor device. 제 1 항에 있어서, 상기 리이드의 변형 및 본딩성을 향상시키기 위하여 4개 이상의 지지를 갖는 것을 특징으로 하는 반도체 장치.The semiconductor device according to claim 1, further comprising four or more supports for improving the deformation and bonding properties of the leads. 제 1 항에 있어서, 상기 절연체는 폴리이미드계 수지인 반도체 장치The semiconductor device according to claim 1, wherein the insulator is a polyimide resin. 제 2 항에 있어서, 상기 4개 이상의 지지대는 열경화성 폴리이미드계 수지를 적층한 다음 접착제로 이루어지는 것을 특징으로 하는 반도체 장치.The semiconductor device according to claim 2, wherein the four or more supports are made of an adhesive after laminating a thermosetting polyimide resin. 제 1 항에 있어서, 상기 금속 와이어는 금 와이어인 것을 특징으로 하는 반도체 장치.The semiconductor device according to claim 1, wherein the metal wire is a gold wire. 주변에 회로와 외부단자가 형성된 사격형상의 반도체 칩, 절연체로 접착된 내부 리이드와 외부 리이드가 윗쪽에 탑재된 반도체 칩의 배열 형태에 따라 사각형으로 되는 여러개의 리이드, 반도체 칩과 리이드를 전기적으로 전속하기 위한 금속 와이어, 상기 반도체 칩과 절연체를 접속하기 위한 제1의 접착층, 상기 절연체와 내부 리이드를 접속하기 위한 제2의 접착층, 상기 반도체칩·제1 및 제2의 접착층·절연체·내부 리이드·금속 와이어를 봉하여 막기 위한 봉지재로 되는 반도체 장치에 있어서, 상기 외부단자는 네 변에 배치되고, 내부 리이드의 앞끝은 반도체 칩 중앙 부근까지 근접하여 배치되는 것을 특징으로 하는 반도체 장치.Shooting semiconductor chips with circuits and external terminals in the periphery, several leads that are rectangular in shape according to the arrangement of semiconductor chips with inner leads bonded to insulators and external leads mounted on top, and electrically transferring semiconductor chips and leads A metal wire for connection, a first adhesive layer for connecting the semiconductor chip and an insulator, a second adhesive layer for connecting the insulator and an inner lead, the semiconductor chip, the first and second adhesive layers, an insulator, an inner lead, A semiconductor device comprising an encapsulant for sealing and blocking a metal wire, wherein the external terminal is disposed on four sides, and the front end of the inner lead is disposed close to the center of the semiconductor chip. 주변에 회로와 외부단자가 형성된 사각형상의 반도체 칩, 절연체로 접착된 내부 리이드와 외부 리이드가 윗족에 탑재된 반도체 칩의 배열형태에 따라 사각형으로 되는 여러개의 리이드, 반도체 칩과 리이드를 전기적으로 접속하기 위한 금속 와이어, 반도체칩·절연체·내부 리이드·금속 와이어를 봉하여 막기 위한 봉지재로 이루어지는 반도체 장치에 잇어서, 처음에 지지대까지 내부 리이드를 식각하고 내부 리이드 본딩 부위에는 플레이팅을 실시한 후, 리이드 프레임 뒷면에 테이프를 부착하고 지지대와 내부 리이드 본딩 부분을 스탬핑 또는 식각하여 자르는 것을 특징으로 하는 반도체 장치의 제조방법.Rectangle-shaped semiconductor chips with circuits and external terminals in the periphery, internal leads bonded with insulators, and multiple leads that are rectangular in shape depending on the arrangement of the semiconductor chips mounted on the upper group. A semiconductor device comprising a metal wire, a semiconductor chip, an insulator, an inner lead, and an encapsulant for sealing and blocking a metal wire. A method of manufacturing a semiconductor device, characterized in that the tape is attached to the back side and the support and the inner lead bonding portion are cut by stamping or etching.
KR1019910023895A 1991-12-23 1991-12-23 Semiconductor device and manufacturing method thereof Expired - Fee Related KR950000278B1 (en)

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KR950000278B1 true KR950000278B1 (en) 1995-01-12

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