KR960020007A - 하이브리드 주파수 합성기 - Google Patents

하이브리드 주파수 합성기 Download PDF

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KR960020007A
KR960020007A KR1019940031319A KR19940031319A KR960020007A KR 960020007 A KR960020007 A KR 960020007A KR 1019940031319 A KR1019940031319 A KR 1019940031319A KR 19940031319 A KR19940031319 A KR 19940031319A KR 960020007 A KR960020007 A KR 960020007A
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South Korea
Prior art keywords
phase
phase accumulator
frequency synthesizer
accumulator
synthesizer
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KR1019940031319A
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KR960016812B1 (ko
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정용주
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양승택
재단법인 한국전자통신연구소
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Priority to KR1019940031319A priority Critical patent/KR960016812B1/ko
Priority to US08/522,702 priority patent/US5656976A/en
Publication of KR960020007A publication Critical patent/KR960020007A/ko
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/1806—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop the frequency divider comprising a phase accumulator generating the frequency divided signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B28/00—Generation of oscillations by methods not covered by groups H03B5/00 - H03B27/00, including modification of the waveform to produce sinusoidal oscillations

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

본 발명은 직접주파수합성기(DDS)와 PLL 합성기를 혼합한 하이브리드 주파수 합성기에 관한 것이다.
본 발명의 구성중 직접주파수합성기는 제1위상누적기 이외에도 K/N인 위상 데이타가 입력되고 상기 제1위상누적기 보다 N배 빠른 클럭으로 동작하는 제2위상누적기(21), 두 위상누적기의 출력을 합산하여 그 결과가 360°가 되는 시점을 검출하여 초기화 회로에 공급하는 360°검출부 및 두 위상누적기의 상태를 초기화하고 초기화된 시점에서 다시 출력주파수의 다음 주기를 합성하도록 제1위상누적기의 출력 타이밍을 조절하는 초기화 회로로 구성되는 것을 특징으로 하며, 상기 본 발명에 의해 장치의 소형화가 가능하여 경제적이다.

Description

하이브리드 주파수 합성기
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 구성도.

Claims (1)

  1. 기준 주파수를 합성하는 직접주파수합성기(DDS)와 분주비가 N으로 고정된 위상 동기 루프(PLL)합성기를 혼합한 하이브리드주파수 합성기에 있어서, 직접주파수합성기는 디지탈 형태로 입력되는 순시 위상 데이터 K를 매 클럭마다 누적시키는 제1위상누적기(20) 이외에도, K/N인 위상 데이타가 입력되고, 상기 제1이상누적기(21) 보다 N배 빠른 클럭으로 동작하는 제2위상누적기(21); 상기 제1위상누적기(20)와 제2위상누적기(21)의 출력을 합산하므로 두 위상누적기의 출력의 합이 360°가 되는 시점을 검출하여, 초기화 회로에 공급하는 360°검출부(22); 및 상기 제1위상누적기(20)와 제2위상누적기(21)의 상태를 초기화하고 초기화된 시점에서 다시 출력주파수의 다음 주기를 합성하도록 제1위상누적기(20)의 출력 타이밍을 조절하는 초기화 회로(23)로 구성되는 것을 특징으로 하는 하이브리드 주파수 합성기.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940031319A 1994-11-26 1994-11-26 하이브리드 주파수 합성기(Hybrid Frequency Synthesizer) Expired - Fee Related KR960016812B1 (ko)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019940031319A KR960016812B1 (ko) 1994-11-26 1994-11-26 하이브리드 주파수 합성기(Hybrid Frequency Synthesizer)
US08/522,702 US5656976A (en) 1994-11-26 1995-09-01 Hybrid frequency synthesizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940031319A KR960016812B1 (ko) 1994-11-26 1994-11-26 하이브리드 주파수 합성기(Hybrid Frequency Synthesizer)

Publications (2)

Publication Number Publication Date
KR960020007A true KR960020007A (ko) 1996-06-17
KR960016812B1 KR960016812B1 (ko) 1996-12-21

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KR1019940031319A Expired - Fee Related KR960016812B1 (ko) 1994-11-26 1994-11-26 하이브리드 주파수 합성기(Hybrid Frequency Synthesizer)

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US (1) US5656976A (ko)
KR (1) KR960016812B1 (ko)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010069610A (ko) * 2001-04-20 2001-07-25 유흥균 고속 저전력 직접 디지털 주파수 합성기 구동형 위상 고정루프(DDFS-driven PLL) 주파수 합성기 설계 기술
KR20010069612A (ko) * 2001-04-20 2001-07-25 유흥균 초고속 디지탈 하이브리드 주파수 합성기 설계 기술
KR20020065430A (ko) * 2002-07-03 2002-08-13 유흥균 위상누적기를 이용한 새로운 디지탈 주파수 합성기설계방법 및 장치 구성

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3159238B2 (ja) * 1996-09-17 2001-04-23 日本電気株式会社 数値制御発振回路
DE19727810C1 (de) * 1997-06-30 1999-02-18 Siemens Ag Hochfrequenz-Signalgenerator
US6748407B1 (en) * 1999-02-03 2004-06-08 Nec Corporation Direct digital synthesizer
US6621860B1 (en) * 1999-02-08 2003-09-16 Advantest Corp Apparatus for and method of measuring a jitter
WO2000054401A1 (de) * 1999-03-11 2000-09-14 Siemens Aktiengesellschaft Verfahren zum erzeugen eines signals mit einstellbarer frequenz durch einen zittersignalgenerator
US6674818B1 (en) 2000-04-17 2004-01-06 Rf Micro Devices, Inc. Reduced complexity decision circuitry
US6693954B1 (en) 2000-04-17 2004-02-17 Rf Micro Devices, Inc. Apparatus and method of early-late symbol tracking for a complementary code keying receiver
US6661834B1 (en) * 2000-04-17 2003-12-09 Rf Micro Devices, Inc. Carrier recovery for spread spectrum communications
EP1301992A1 (en) * 2000-07-10 2003-04-16 Ciena Corporation Frequency synthesizer
EP1518323B1 (en) * 2002-06-19 2006-11-02 R & C Holding ApS Phase-locked loop with incremental phase detectors and a converter for combining a logical operation with a digital to analog conversion
US7336748B2 (en) * 2003-12-23 2008-02-26 Teradyne, Inc. DDS circuit with arbitrary frequency control clock
KR102671500B1 (ko) * 2021-12-13 2024-05-31 한국항공우주연구원 직접 디지털 주파수 합성기의 제어 방법 및 직접 디지털 주파수 합성기

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5028887A (en) * 1989-08-31 1991-07-02 Qualcomm, Inc. Direct digital synthesizer driven phase lock loop frequency synthesizer with hard limiter
US4965533A (en) * 1989-08-31 1990-10-23 Qualcomm, Inc. Direct digital synthesizer driven phase lock loop frequency synthesizer
US4992743A (en) * 1989-11-15 1991-02-12 John Fluke Mfg. Co., Inc. Dual-tone direct digital synthesizer
GB2258774B (en) * 1991-08-16 1994-12-07 Marconi Instruments Ltd Waveform generators
US5382913A (en) * 1993-03-29 1995-01-17 Motorola, Inc. Method and apparatus for generating two phase-coherent signals with arbitrary frequency ratio

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010069610A (ko) * 2001-04-20 2001-07-25 유흥균 고속 저전력 직접 디지털 주파수 합성기 구동형 위상 고정루프(DDFS-driven PLL) 주파수 합성기 설계 기술
KR20010069612A (ko) * 2001-04-20 2001-07-25 유흥균 초고속 디지탈 하이브리드 주파수 합성기 설계 기술
KR20020065430A (ko) * 2002-07-03 2002-08-13 유흥균 위상누적기를 이용한 새로운 디지탈 주파수 합성기설계방법 및 장치 구성

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US5656976A (en) 1997-08-12
KR960016812B1 (ko) 1996-12-21

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