KR970052911A - 반도체 소자의 평탄화 방법 - Google Patents

반도체 소자의 평탄화 방법 Download PDF

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Publication number
KR970052911A
KR970052911A KR1019950065696A KR19950065696A KR970052911A KR 970052911 A KR970052911 A KR 970052911A KR 1019950065696 A KR1019950065696 A KR 1019950065696A KR 19950065696 A KR19950065696 A KR 19950065696A KR 970052911 A KR970052911 A KR 970052911A
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KR
South Korea
Prior art keywords
oxide film
plasma cvd
cvd process
density plasma
high density
Prior art date
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Ceased
Application number
KR1019950065696A
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English (en)
Inventor
배영백
Original Assignee
김주용
현대전자산업 주식회사
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Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950065696A priority Critical patent/KR970052911A/ko
Publication of KR970052911A publication Critical patent/KR970052911A/ko
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/092—Manufacture or treatment of dielectric parts thereof by smoothing the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H10P14/6923—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG

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  • Formation Of Insulating Films (AREA)

Abstract

본 발명은 반도체 소자의 평탄화 방법을 제공하는 것으로, 금속층상에 형성된 산화막을 고밀도 플라즈마 CVD공정으로 상기 산화막의 중착 및 식각을 동시에 실시하여 평탄화시킬 수 있도록 하므로써 높은 산화막밀도 및 수분방지 특성이 우수하고, 높은 중착비를 가지며 갭필링까지 되므로 소자의 수율을 향상시킬 수 있다.
※선택도 : 제2D도.

Description

반도체 소자의 평탄화 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 고밀도 플라즈마 CVD 공정에 의한 중착비 및 식각비를 각도에 대하여 도시한 그래프도.

Claims (5)

  1. 절연막이 형성된 실리콘기판상에 금속층을 패터닝하는 단계와, 상기 단계로부터 상기 실리콘기판이 전체 상부면에 산화막을 형성한 후 고밀도 플라즈마 CVD공정으로 상기 산화막을 평탄화하는 단계로 이루는 것을 특징으로 하는 반도체 소자의 평탄화 방법.
  2. 제1항에 있어서 상기 절연막은 BPSG로 이루어지는 것을 특징으로 하는 반도체 소자의 평탄화 방법.
  3. 제1항에 있어서, 상기 고밀도 플라즈마 CVD 공정은 증착 및 식각이 동시에 이루어지는 것을 특징으로 하는 반도체 소자의 평탄화 방법.
  4. 제1항에 있어서, 상기 고밀도 플라즈마 CVD 공정은 SiH4및 O2가스를 이용하여 실시하는 것을 특징으로 하는 반도체 소자의 평탄화 방법.
  5. 제1항에 있어서, 상기 고밀도 플라즈마 CVD 공정은 45 내지 50°의 입사각으로 실시하는 것을 특징으로 하는 반도체 소자의 평탄화 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950065696A 1995-12-29 1995-12-29 반도체 소자의 평탄화 방법 Ceased KR970052911A (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950065696A KR970052911A (ko) 1995-12-29 1995-12-29 반도체 소자의 평탄화 방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950065696A KR970052911A (ko) 1995-12-29 1995-12-29 반도체 소자의 평탄화 방법

Publications (1)

Publication Number Publication Date
KR970052911A true KR970052911A (ko) 1997-07-29

Family

ID=66624160

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950065696A Ceased KR970052911A (ko) 1995-12-29 1995-12-29 반도체 소자의 평탄화 방법

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KR (1) KR970052911A (ko)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5895821A (ja) * 1981-11-30 1983-06-07 Mitsubishi Electric Corp 平行平板型プラズマｃｖｄ法
JPS6450429A (en) * 1987-08-20 1989-02-27 Semiconductor Energy Lab Formation of insulating film
JPH01209728A (ja) * 1988-02-17 1989-08-23 Mitsubishi Electric Corp 絶縁保護膜の形成方法
JPH03280539A (ja) * 1990-03-29 1991-12-11 Fuji Electric Co Ltd 絶縁膜を備えた半導体装置の製造方法
JPH04144231A (ja) * 1990-10-05 1992-05-18 Nec Corp 半導体装置の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5895821A (ja) * 1981-11-30 1983-06-07 Mitsubishi Electric Corp 平行平板型プラズマｃｖｄ法
JPS6450429A (en) * 1987-08-20 1989-02-27 Semiconductor Energy Lab Formation of insulating film
JPH01209728A (ja) * 1988-02-17 1989-08-23 Mitsubishi Electric Corp 絶縁保護膜の形成方法
JPH03280539A (ja) * 1990-03-29 1991-12-11 Fuji Electric Co Ltd 絶縁膜を備えた半導体装置の製造方法
JPH04144231A (ja) * 1990-10-05 1992-05-18 Nec Corp 半導体装置の製造方法

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