KR970052995A - 반도체소자의 트리플웰 형성방법 - Google Patents

반도체소자의 트리플웰 형성방법 Download PDF

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KR970052995A
KR970052995A KR1019950068661A KR19950068661A KR970052995A KR 970052995 A KR970052995 A KR 970052995A KR 1019950068661 A KR1019950068661 A KR 1019950068661A KR 19950068661 A KR19950068661 A KR 19950068661A KR 970052995 A KR970052995 A KR 970052995A
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well
ion implantation
photoresist
oxide film
energy
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KR1019950068661A
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KR0167303B1 (ko
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이상돈
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문정환
Lg 반도체 주식회사
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Priority to KR1019950068661A priority Critical patent/KR0167303B1/ko
Priority to US08/772,289 priority patent/US5927991A/en
Priority to JP8348086A priority patent/JP2990498B2/ja
Priority to DE19654686A priority patent/DE19654686C2/de
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0125—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics
    • H10W10/0126—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers
    • H10W10/0127—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers using both n-type and p-type impurities, e.g. for isolation of complementary doped regions

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

본 발명은 필드산화(field oxidation)후에 질화막을 제거하지 않고 그대로 둔 상태에서 실드(shield) 및 웰 이온주입을 실시함으로써 래치-업(Latch-up) 특성을 개선할 수 있고 고립특성을 개선할 수 있도록 된 반도체소자의 트리플웰 형성방법에 관한 것으로, (a) 실리콘기판(11)상에 패드산화막(12)과, CVD질화막(13)을 증착한 후, 포토리소그래피 공정에 의해 상기 질화막(13)의 일정영역을 에치하고, 필드산화막(14)을 성장시키고, 고에너지 n-실드 이온주입을 수행하는 공정, (b) 포토레지스터(16)를 형성한 후, 일정영역을 구분하고 상기 n-실드 이온주입깊이까지 고에너지 p웰 이온주입을 수행하는 공정, (c) 상기 포토레지스트(16)을 제거한 후, 새로운 포토레지스트(18)을 형성한 후, 공통 p웰 및 실드 p웰을 정의하는 p웰 마스크로 상기 포토레지스트(18)을 사용하여, 중간(medium) 및 저(low) 에너지 p 웰 이온주입을 하는 공정, (d) 상기 포토레지스트(18)를 제거한 후, 새로운 포토 레지스트(21)를 형성한 후, n웰 마스크로 상기 포토레지스트(21)을 사용하여, 중간(medium) 및 저(low) 에너지 n웰 이온주입을 하고, 상기 포토레지스트(21)를 제거하고, 질화막(13)과 패드산화막(12)을 제거한 후, 어닐(anneal)공정을 포함한다.

Description

반도체소자의 트리플웰 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도 a 내지 e는 본 발명에 따른 트리플 웰 제조방법을 나타낸 종단면도.

Claims (7)

  1. (가) 실리콘기판(11)상에 패드산화막(12)과, CVD질화막(13)을 증착한 후, 포토리소그래피공정에 의해 상기 질화막(13)의 일정영역을 에치하고, 필드산화막(14)을 성장시키고, 고에너지 n-실드 이온주입을 수행하는 공정, (나) 포토레지스트(16)를 형성한 후, 일정영역을 구분하고 상기 n-실드 이온주입깊이까지 고에너지 p웰 이온주입을 수행하는 공정, (다) 상기 포토레지스트(16)를 제거한 후, 새로운 포토레지스트(18)를 형성한 후, 공통 p웰 및 실드 p웰을 정의하는 p웰 마스크로 상기 포토레지스트(18)을 사용하여, 중간(medium) 및 저(low) 에너지 p웰이온주입을 하는 공정, (라) 상기 포토레지스트(18)를 제거한 후, 새로운 포토레지스트(21)를 형성한 후, n웰 마스크로 상기 포토레지스트(21)을 사용하여, 중간(medium) 및 저(low) 에너지 n웰 이온주입을 하고, 상기 포토레지스트(21)을 제거하고, 질화막(13)과 패드산화막(12)을 제거하고, 어닐링(annealing)시키는 공정을 포함하는 것을 특징으로 하는 반도체소자의 트리플웰 형성방법.
  2. 제1항에 있어서, 고에너지 이온 주입은 0.5∼4.0 MeV 에너지범위이고, 불순물(Dose)은 1012∼1014의 범위이고, 또한 중간 에너지 이온주입은 0.1∼4.0MeV의 에너지 범위이며, 불순물은 1012∼1014의 범위인 것을 특징으로하는 반도체소자의 트리플웰 형성방법.
  3. 제1항에 있어서, 저에너지 이온주입은 불순물이 필드산화막 하면에 위치할 수 있도록 필드산화막 두께에 따라 에너지를 조절하며, 불순물은 1011-1014의 범위인 것을 특징으로 하는 반도체소자의 트리플웰 형성방법.
  4. 제1항에 있어서, 중간 및 저에너지 이온주입은 한 번만 이온주입을하여 웰을 형성하는 것을 특징으로 하는 반도체소자의 트리플웰 형성방법.
  5. 제1항에 있어서, 질화막의 두께는 저에너지 이온주입으로 불순물들을 필드 산화막 하면에 위치시킬 때 채널영역의 원하는 위치에 불순물들을 위치시킬 수 있도록 조절가능한 것을 특징으로 하는 반도체소자의 트리플웰 형성방법.
  6. 제1항에 있어서, 상기 실리콘기판(11)은 p형실리콘기판인 것을 특징으로 하는 반도체소자의 트리플웰 형성방법.
  7. 제1항에 있어서, p웰 및 n웰 마스크를 사용하여 중간 및 저에너지로 각각 p웰 및 n웰 이온주입을 한 후 문턱전압(Vt) 조절 이온주입을 하는 것을 특징으로 하는 반도체소자의 트리플웰 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950068661A 1995-12-30 1995-12-30 반도체소자의 트리플웰 형성방법 Expired - Lifetime KR0167303B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019950068661A KR0167303B1 (ko) 1995-12-30 1995-12-30 반도체소자의 트리플웰 형성방법
US08/772,289 US5927991A (en) 1995-12-30 1996-12-23 Method for forming triple well in semiconductor device
JP8348086A JP2990498B2 (ja) 1995-12-30 1996-12-26 半導体素子の三重ウェル形成方法
DE19654686A DE19654686C2 (de) 1995-12-30 1996-12-30 Verfahren zum Herstellen einer Dreiwannen-Anordnung in einer Halbleitervorrichtung

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KR1019950068661A KR0167303B1 (ko) 1995-12-30 1995-12-30 반도체소자의 트리플웰 형성방법

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KR970052995A true KR970052995A (ko) 1997-07-29
KR0167303B1 KR0167303B1 (ko) 1999-02-01

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JP (1) JP2990498B2 (ko)
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DE (1) DE19654686C2 (ko)

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US6107672A (en) * 1997-09-04 2000-08-22 Matsushita Electronics Corporation Semiconductor device having a plurality of buried wells
DE19752848C2 (de) * 1997-11-28 2003-12-24 Infineon Technologies Ag Elektrisch entkoppelter Feldeffekt-Transistor in Dreifach-Wanne und Verwendung desselben
KR100260559B1 (ko) * 1997-12-29 2000-07-01 윤종용 비휘발성 메모리 장치의 웰 구조 및 그 제조 방법
JP3733252B2 (ja) 1998-11-02 2006-01-11 セイコーエプソン株式会社 半導体記憶装置及びその製造方法
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JP3506025B2 (ja) 1998-11-30 2004-03-15 セイコーエプソン株式会社 半導体記憶装置及びその製造方法
JP4501183B2 (ja) * 1999-09-14 2010-07-14 株式会社デンソー 半導体装置の製造方法
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US7145191B1 (en) * 2000-03-31 2006-12-05 National Semiconductor Corporation P-channel field-effect transistor with reduced junction capacitance
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JP2008153621A (ja) * 2006-11-22 2008-07-03 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP5530086B2 (ja) * 2008-09-26 2014-06-25 ラピスセミコンダクタ株式会社 半導体装置の製造方法

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Publication number Publication date
DE19654686A1 (de) 1997-07-03
JPH09199612A (ja) 1997-07-31
US5927991A (en) 1999-07-27
KR0167303B1 (ko) 1999-02-01
DE19654686C2 (de) 2000-04-27
JP2990498B2 (ja) 1999-12-13

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