KR970053693A - 테 부재로 봉합된 교화체로 약한 장치를 패키지하는 방법 - Google Patents

테 부재로 봉합된 교화체로 약한 장치를 패키지하는 방법 Download PDF

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Publication number
KR970053693A
KR970053693A KR1019960062066A KR19960062066A KR970053693A KR 970053693 A KR970053693 A KR 970053693A KR 1019960062066 A KR1019960062066 A KR 1019960062066A KR 19960062066 A KR19960062066 A KR 19960062066A KR 970053693 A KR970053693 A KR 970053693A
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KR
South Korea
Prior art keywords
sol
weak device
lid member
rim
tool
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1019960062066A
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English (en)
Inventor
토마스 딕슨 두드라르
한병준
벤카타램 레디 라주
죠지 존 쉐브척
Original Assignee
보토스 리챠드 제이
루슨트 테크놀로지스 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 보토스 리챠드 제이, 루슨트 테크놀로지스 인코포레이티드 filed Critical 보토스 리챠드 제이
Publication of KR970053693A publication Critical patent/KR970053693A/ko
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/40—Fillings or auxiliary members in containers, e.g. centering rings
    • H10W76/42—Fillings
    • H10W76/47—Solid or gel fillings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Laminated Bodies (AREA)

Abstract

집적 회로 칩 또는 다칩 어셈블리와 같은 약한 장치(fragile device)는 장치의 측면을 둘러싸고 있는 졸(sol)을 먼저 투입함으로써 패키지된다. 졸은 통상 크리몰드된 플라스틱 물질로 이루어진 테 부재(rim member)에 의해 측방으로 봉합되어 있다. 투입된 졸의 양은 테 부재의 상부에서 흘러 내릴 만큼 충분하지는 않다. 졸은 젤(gel)을 형성하기 위해 가열된다. 양호한 경우에, 덮개 부재는, 예를 들어 약한 장치의 부수적인 기계적 보호목적을 달상하기 위해서 테 부재의 상부면상의 적절한 자리에 위치될 수 있다.

Description

테 부재로 봉합된 교화체로 약한 장치를 패키지하는 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 특성 실시예에 따라 제조된 전자 패키지의 단면도.

Claims (6)

  1. 약한 장치(fragile device)를 패키지하는 방법에 있어서, (a)외부 측면을 갖는 약한 장치(fragile device)를 둘러싸는 소정의 위치에, 통상 프리몰드된 플라스틱 물질로 이루어지며 내부 측면 및 상부면을 갖는 테부재(rim member)를 매치하는 단계와, (b) 상기 약한 장치의 외부 측면의 적어도 일부분을 피막시키기에 충분하지만 상기 테 부재의 상부면 상에서 흘러내리지 않을 정도의 양의 졸 매체(sol medium)를 상기 테 부재의 내부면으로 투입하는 단계와, (c) 상기 졸을 교화체(gel medium)로 변환하기에 충분한 온도가 상기 졸을 가열 하는 단계를 포함하는, 약한 장치 패키지 방법.
  2. 제1항에 있어서, 상기 약한 장치가 반도체 집적 회로 칩을 포함하는, 약한 장치 패키지 방법.
  3. 제2항에 있어서, 단계(c) 다음에는 상기 테 부재 상부에 위치하는 덮개 부재를 배치하는 단계(d)가 이어지는, 약한 장치 패키지 방법.
  4. 제3항에 있어서, 단계(d)가 표준형의 집어서 놓는 기구(a pick-and-place tool)로 수행되고, 덮개 부재가 집어서 놓은 기구와의 저압 접촉 상태를 제공할 수 있는 평탄한 외부의 주요 상부면을 가지고 있는 약한 장치 패키지 방법.
  5. 제1항에 있어서, 단계(c) 다음에는 상기 테 부재 상부에 위치하는 덮개 부재를 배치하는 단계(d)가 이어지는, 약한 장치 패키지 방법.
  6. 제5항에 있어서, 단계(d)가 표준형의 집어서 놓는 기구(a pick-and-place tool)로 수행되고, 덮개 부재가 집어서 놓는 기구와의 저압 접촉 상태를 제공할 수 있는 평탄한 외부의 주요 상부면을 가지고 있는, 약한 장치 패키지 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960062066A 1995-12-05 1996-12-05 테 부재로 봉합된 교화체로 약한 장치를 패키지하는 방법 Withdrawn KR970053693A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US56719395A 1995-12-05 1995-12-05
US08/567,193 1995-12-05

Publications (1)

Publication Number Publication Date
KR970053693A true KR970053693A (ko) 1997-07-31

Family

ID=24266120

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960062066A Withdrawn KR970053693A (ko) 1995-12-05 1996-12-05 테 부재로 봉합된 교화체로 약한 장치를 패키지하는 방법

Country Status (4)

Country Link
EP (1) EP0778616A3 (ko)
JP (1) JPH09232348A (ko)
KR (1) KR970053693A (ko)
CN (1) CN1173737A (ko)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020014688A1 (en) 1999-03-03 2002-02-07 Suresh Ramalingam Controlled collapse chip connection (c4) integrated circuit package which has two dissimilar underfill materials
US6238948B1 (en) * 1999-03-03 2001-05-29 Intel Corporation Controlled collapse chip connection (C4) integrated circuit package that has a fillet which seals an underfill material
US6528345B1 (en) 1999-03-03 2003-03-04 Intel Corporation Process line for underfilling a controlled collapse
US6331446B1 (en) 1999-03-03 2001-12-18 Intel Corporation Process for underfilling a controlled collapse chip connection (C4) integrated circuit package with an underfill material that is heated to a partial gel state
US6774480B1 (en) * 1999-07-30 2004-08-10 Micron Technology, Inc. Method and structure for manufacturing improved yield semiconductor packaged devices
US6700209B1 (en) 1999-12-29 2004-03-02 Intel Corporation Partial underfill for flip-chip electronic packages
CN100336221C (zh) * 2002-11-04 2007-09-05 矽品精密工业股份有限公司 可堆栈半导体封装件的模块化装置及其制法
CN108417540B (zh) * 2018-03-26 2020-10-16 合肥源康信息科技有限公司 一种指纹识别芯片装置
JP7677562B1 (ja) * 2024-09-12 2025-05-15 三菱電機株式会社 半導体装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3919602A (en) * 1972-03-23 1975-11-11 Bosch Gmbh Robert Electric circuit arrangement and method of making the same
JPS59208800A (ja) * 1983-05-12 1984-11-27 株式会社日立製作所 自動車用電子装置
JPS61125142A (ja) * 1984-11-22 1986-06-12 Hitachi Ltd 電子装置
JPH07120733B2 (ja) * 1985-09-27 1995-12-20 日本電装株式会社 車両用半導体素子パッケージ構造とその製造方法
US5241133A (en) 1990-12-21 1993-08-31 Motorola, Inc. Leadless pad array chip carrier
US5324888A (en) * 1992-10-13 1994-06-28 Olin Corporation Metal electronic package with reduced seal width
US5346118A (en) 1993-09-28 1994-09-13 At&T Bell Laboratories Surface mount solder assembly of leadless integrated circuit packages to substrates
US5473512A (en) 1993-12-16 1995-12-05 At&T Corp. Electronic device package having electronic device boonded, at a localized region thereof, to circuit board

Also Published As

Publication number Publication date
EP0778616A3 (en) 1999-03-31
CN1173737A (zh) 1998-02-18
EP0778616A2 (en) 1997-06-11
JPH09232348A (ja) 1997-09-05

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