KR970077199A - Method for forming wiring layer of semiconductor device - Google Patents

Method for forming wiring layer of semiconductor device Download PDF

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Publication number
KR970077199A
KR970077199A KR1019960015596A KR19960015596A KR970077199A KR 970077199 A KR970077199 A KR 970077199A KR 1019960015596 A KR1019960015596 A KR 1019960015596A KR 19960015596 A KR19960015596 A KR 19960015596A KR 970077199 A KR970077199 A KR 970077199A
Authority
KR
South Korea
Prior art keywords
forming
buffer layer
semiconductor device
wiring layer
barrier metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1019960015596A
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Korean (ko)
Inventor
박지순
이장은
김병준
Original Assignee
김광호
삼성전자 주식회사
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019960015596A priority Critical patent/KR970077199A/en
Publication of KR970077199A publication Critical patent/KR970077199A/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/036—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being within a main fill metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명에 의한 반도체 소자의 배선층 형성 방법은 배리어 메탈상에 Si이 함유된 금속막으로 버퍼층을 형성한 후 CVD-W막을 형성함으로써, 스몰(small) 콘택을 갖는 고단차 구조의 반도체 소자에서 밀착층의 취약한 단차 도포성으로 인해 콘택홀 바닥에 계면 결함(Interfacial Defect, 예를 들어 윔홀(Worm Hole))이 발생하는 것을 막고, 이로 인해 양호한 전기적 특성을 얻을 수 있다는 장점이 있다.In the method for forming a wiring layer of a semiconductor device according to the present invention, a buffer layer is formed of a metal film containing Si on a barrier metal and then a CVD-W film is formed. In the semiconductor element having a high- (Worm Hole) is prevented from occurring at the bottom of the contact hole due to the weak step coverage of the contact hole, thereby obtaining good electrical characteristics.

Description

반도체 소자의 배선층 형성방법Method for forming wiring layer of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2도 내지 제4도는 본 발명에 의한 반도체 소자의 배선층 형성 방법을 순차적으로 도시한 단면도들이다.FIGS. 2 to 4 are sectional views sequentially showing a method for forming a wiring layer of a semiconductor device according to the present invention.

Claims (6)

반도체 기판에 소오스/드레인 영역을 형성하는 제1단계; 상기 소오스/드레인 영역이 형성된 반도체 기판에 절연막을 증착하는 제2단계; 상기 소오스/드레인 영역 상부의 상기 절연막을 식각하여 콘택홀을 형성하는 제3단계; 상기 결과물에 배리어 메탈(barrier metal)층 및 버퍼(buffer)층을 차례로 얇게 형성하는 제4단계; 화학 기상 증착(CVD; Chemical Vapor Deposition)공정으로 상기 결과물 전면에 텅스텐(W)을 증착하는 제5단계를 포함하는 것을 특징으로 하는 반도체 소자의 배선층 형성 방법.A first step of forming a source / drain region in a semiconductor substrate; A second step of depositing an insulating film on the semiconductor substrate on which the source / drain regions are formed; A third step of forming a contact hole by etching the insulating film on the source / drain region; A fourth step of forming a barrier metal layer and a buffer layer in this order on the resultant structure; And a fifth step of depositing tungsten (W) on the entire surface of the resultant by a chemical vapor deposition (CVD) process. 제1항에 있어서, 상기 배리어 메탈(barrier metal)층은 TiN, Ti, Ti/TiN, WSiX중에서 어느 하나를 사용하는 것을 특징으로 하는 반도체 소자의 배선층 형상 방법.The method according to claim 1, wherein the barrier metal layer is formed of any one of TiN, Ti, Ti / TiN, and WSi x . 제1항에 있어서, 상기 버퍼(buffer)층은 Si를 함유한 금속막을 사용하는 것을 특징으로 하는 반도체 소자의 배선층 형성 방법.The method according to claim 1, wherein the buffer layer uses a metal film containing Si. 제1항에 있어서, 상기 버퍼(buffer)층의 두께는 500A 이하인 것을 특징으로 하는 반도체 소자의 배선층 형성 방법.2. The method according to claim 1, wherein the thickness of the buffer layer is 500 A or less. 제1항에 있어서, 상기 제4단계에서 상기 버퍼층상에 배리어 메탈층을 추가로 형성하는 것을 특징으로 하는 반도체 소자의 배선층 형성 방법.The method according to claim 1, further comprising forming a barrier metal layer on the buffer layer in the fourth step. 제1항에 있어서, 상기 제5단계를 실시하기 전에 상기 제4단계를 반복하는 것을 특징으로 하는 반도체 소자의 배선층 형성 방법.The method according to claim 1, wherein the fourth step is repeated before the fifth step is performed. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960015596A 1996-05-11 1996-05-11 Method for forming wiring layer of semiconductor device Withdrawn KR970077199A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960015596A KR970077199A (en) 1996-05-11 1996-05-11 Method for forming wiring layer of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960015596A KR970077199A (en) 1996-05-11 1996-05-11 Method for forming wiring layer of semiconductor device

Publications (1)

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KR970077199A true KR970077199A (en) 1997-12-12

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KR1019960015596A Withdrawn KR970077199A (en) 1996-05-11 1996-05-11 Method for forming wiring layer of semiconductor device

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KR (1) KR970077199A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100906307B1 (en) * 2002-11-21 2009-07-07 매그나칩 반도체 유한회사 Manufacturing Method of Semiconductor Device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100906307B1 (en) * 2002-11-21 2009-07-07 매그나칩 반도체 유한회사 Manufacturing Method of Semiconductor Device

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