KR970077604A - Improved semiconductor chip package and manufacturing method thereof - Google Patents

Improved semiconductor chip package and manufacturing method thereof Download PDF

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Publication number
KR970077604A
KR970077604A KR1019960017947A KR19960017947A KR970077604A KR 970077604 A KR970077604 A KR 970077604A KR 1019960017947 A KR1019960017947 A KR 1019960017947A KR 19960017947 A KR19960017947 A KR 19960017947A KR 970077604 A KR970077604 A KR 970077604A
Authority
KR
South Korea
Prior art keywords
semiconductor chip
metal layer
chip package
insulator
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1019960017947A
Other languages
Korean (ko)
Inventor
서동수
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019960017947A priority Critical patent/KR970077604A/en
Publication of KR970077604A publication Critical patent/KR970077604A/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/811—Multiple chips on leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/04—Manufacture or treatment of leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/411—Chip-supporting parts, e.g. die pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/016—Manufacture or treatment using moulds

Landscapes

  • Wire Bonding (AREA)

Abstract

본 발명은 반도체 칩 패키지에 관한 것으로, 더욱 상세하게는 반도체 조립 공정의 와이어 본딩 공정에 사용되는 와이어의 길이를 줄임으로써 몰딩 공정에서 성형 수지의 흐름으로 인하여 와이어가 스위핑(sweeping)되는 것을 방지할 수 있는 개선된 반도체 칩 패키지와 그 제조 방법에 관한 것이다.The present invention relates to a semiconductor chip package, and more particularly, to a semiconductor chip package capable of preventing a wire from sweeping due to a flow of molding resin in a molding process by reducing a length of a wire used in a wire bonding process of a semiconductor assembly process The present invention relates to an improved semiconductor chip package and a manufacturing method thereof.

Description

개선된 반도체 칩 패키지와 그 제조 방법Improved semiconductor chip package and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2도 (A), (B)는 본 발명에 의한 개선된 반도체 칩 패키지의 내부 구조를 나타낸 평면도, (C)는 (B)의 단면도이며, (D)는 (C)의 A부분을 확대하여 도시한 단면도.(A) is a plan view showing an internal structure of an improved semiconductor chip package according to the present invention, (C) is a sectional view of (B), Fig.

Claims (4)

다이 패드와 복수개의 인너 리드와 반도체 칩으로 이루어진 반도체 칩 패키지에 있어서, 상기 다이 패드의 상부면에는 절연체가 형성되어 있고, 본딩 패드를 갖는 상기 반도체 칩은 접착제에 의해 상기 본eld 패드가 상기 절연체에 대향하도록 상기 절연체에 부착되어 있으며, 상기 본딩 패드에 대향하는 상기 절연체상의 소정 부위에는 메탈층이 형성되며, 상기 본딩 패드와 상기 메탈층은 연결 수단에 의해 전기적으로 연결되며 상기 메탈층과 상기 인너리드는 도전성의 와이어로 연결된 것을 특징으로 하는 개선된 반도체 칩 패키지.A semiconductor chip package comprising a die pad and a plurality of inner leads and a semiconductor chip, wherein an insulator is formed on an upper surface of the die pad, and the semiconductor chip having a bonding pad is bonded to the insulator And a metal layer is formed on a predetermined portion of the insulator opposite to the bonding pad. The bonding pad and the metal layer are electrically connected to each other by connecting means, and the metal layer and the inner lead Are connected by a conductive wire. 제1항에 있어서, 상기 연결 수단은 이방성 도전체인 것을 특징으로 하는 개선된 반도체 칩 패키지.The improved semiconductor chip package of claim 1, wherein the connecting means is an anisotropic conductive. 제1항에 있어서, 상기 접착제는 재질이 에폭시인 것을 특징으로 하는 개선된 반도체 칩 패키지.The improved semiconductor chip package of claim 1, wherein the adhesive is epoxy. 반도체 칩의 본딩 패드에 대향하는 가장자리 부분에 메탈층이 형성된 절연체를 접착시키는 단계와, 상기 반도체 칩의 본딩 패드가 상기 메탈층과 대향하도록 상기 반도체 칩을 상기 절연체에 접착시키는 단계와, 상기 본딩 패드와 상기 메탈층을 전기적으로 연결시키는 단계와, 상기 메탈층을 상기 리드 프레임의 인너 리드에 연결시키는 단계와, 성형 수지로 몰딩하는 단계로 이루어진 것을 특징으로 하는 개선된 반도체 칩 패키지 제조 방법.A method of manufacturing a semiconductor device, comprising the steps of: bonding an insulator having a metal layer formed on an edge portion thereof opposite to a bonding pad of a semiconductor chip; bonding the semiconductor chip to the insulator such that the bonding pad of the semiconductor chip faces the metal layer; And connecting the metal layer to the inner lead of the lead frame; and molding the metal layer with a molding resin. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960017947A 1996-05-27 1996-05-27 Improved semiconductor chip package and manufacturing method thereof Withdrawn KR970077604A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960017947A KR970077604A (en) 1996-05-27 1996-05-27 Improved semiconductor chip package and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960017947A KR970077604A (en) 1996-05-27 1996-05-27 Improved semiconductor chip package and manufacturing method thereof

Publications (1)

Publication Number Publication Date
KR970077604A true KR970077604A (en) 1997-12-12

Family

ID=66219639

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960017947A Withdrawn KR970077604A (en) 1996-05-27 1996-05-27 Improved semiconductor chip package and manufacturing method thereof

Country Status (1)

Country Link
KR (1) KR970077604A (en)

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