KR970077985A - High-pass IIR filter design method and high pass IIR filter - Google Patents

High-pass IIR filter design method and high pass IIR filter Download PDF

Info

Publication number
KR970077985A
KR970077985A KR1019960017472A KR19960017472A KR970077985A KR 970077985 A KR970077985 A KR 970077985A KR 1019960017472 A KR1019960017472 A KR 1019960017472A KR 19960017472 A KR19960017472 A KR 19960017472A KR 970077985 A KR970077985 A KR 970077985A
Authority
KR
South Korea
Prior art keywords
output
adder
shifter
delay
delay unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
KR1019960017472A
Other languages
Korean (ko)
Other versions
KR0176205B1 (en
Inventor
이제석
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019960017472A priority Critical patent/KR0176205B1/en
Publication of KR970077985A publication Critical patent/KR970077985A/en
Application granted granted Critical
Publication of KR0176205B1 publication Critical patent/KR0176205B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0223—Computation saving measures; Accelerating measures
    • H03H17/0227—Measures concerning the coefficients
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0223—Computation saving measures; Accelerating measures
    • H03H17/0225—Measures concerning the multipliers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0223—Computation saving measures; Accelerating measures
    • H03H17/0238—Measures concerning the arithmetic used
    • H03H17/0241—Distributed arithmetic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H2017/0072—Theoretical filter design
    • H03H2017/009—Theoretical filter design of IIR filters

Landscapes

  • Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Filters That Use Time-Delay Elements (AREA)
  • Picture Signal Circuits (AREA)

Abstract

본 발명은 고역통과 IIR 필터의 설계 방법 및 이에 적합한 고역통과 IIR 필터를 개시한다. 본 발명의 장치는 디지탈 신호 x(n)를 입력받아 소정시간 지연시키는 지연기(21)와, 지연기(21)의 출력을 MSB 측으로 1비트 시프트하는 시프터(22)와, 지연기(21)의 출력을 소정시간 지연시키는 지연기(23)와, 디지탈 신호 y(n)을 입력받아 소정시간 지연시키는 지연기(24)와, 지연기(24)의 출력을 MSB 측으로 2비트 시프트하는 시프터(25)와, 지연기(24)의 출력을 소정시간 지연시키는 지연기(26)와, 지연기(23)의 출력과 시프터(25)의 출력을 가산하는 가산기(100)와, 가산기(100)의 출력에서 시프터(22)의 출력을 감산하는 감산기(200)와, 디지탈 신호 x(n)와 감산기(200)의 출력을 가산하는 가산기(300)와, 가산기(300)의 출력과 계수 c를 승산하는 승산기(A)와, 지연기(24)의 출력과 지연기(26)의 출력을 가산하는 가산기(400)와, 가산기(400)의 출력과 계수 2t를 승산하는 승산기(B)와, 승산기(A)의 출력에서 승산기(B)의 출력을 감산하는 감산기(500)와, 감산기(500)의 출력과 지연기(26)의 출력을 가산하는 가산기(600)로 구성된다. 여기서,WD는 임계 주파수, T는 샘플링 시간이다. 따라서, 본 발명은 승산기의 갯수가 감소함으로 인하여 하드웨어의 크기가 작아지는 이점이 있다.The present invention discloses a method of designing a high-pass IIR filter and a high-pass IIR filter suitable therefor. The apparatus includes a delay unit 21 for receiving a digital signal x (n) and delaying the digital signal x (n) for a predetermined time, a shifter 22 for shifting the output of the delay unit 21 by one bit toward the MSB, A delay unit 24 for delaying the output of the delay unit 24 by 2 bits to the MSB side, a delay unit 23 for delaying the output of the delay unit 24 by a predetermined time, An adder 100 for adding the output of the delay unit 23 and the output of the shifter 25 to the output of the adder 100, A subtractor 200 for subtracting the output of the shifter 22 from the output of the adder 300 and an adder 300 for adding the output of the subtracter 200 to the digital signal x A multiplier B for multiplying an output of the adder 400 by a coefficient 2t, a multiplier B for multiplying the output of the adder 400 by a coefficient 2t, Win It consists of an adder 600 for adding the output of the group (A) output and the retarder (26) of the subtracter 500, a subtractor 500 for subtracting the output of the multiplier (B) at the output of the. here, W D is the threshold frequency, and T is the sampling time. Therefore, the present invention has an advantage that the size of the hardware is reduced because the number of multipliers is reduced.

Description

고역통과 IIR 필터의 설계 방법 및 이에 적합한 고역통과 IIR 필터High-pass IIR filter design method and high pass IIR filter

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제 2 도는 본 발명에 의한 고역통과 IIR 필터의 구성을 보인 도면.FIG. 2 is a diagram showing a configuration of a high-pass IIR filter according to the present invention; FIG.

Claims (2)

임계 주파수(WD)와 샘플링 주기(T)를 입력받아 아날로그 주파수(WA)를 계산하는 제 1 단계 ; 아날로그 영역에서의 시스템 전달 함수(H(S))를 바이리니어 변환법에 의하여 디지탈 영역에서의 시스템 전달 함수(H(Z))로 변환하는 제 2 단계 ; 상기 제 2 단계에서 구한 디지탈 영역에서의 시스템 전달 함부(H(Z))로부터 차분 방정식(y(n))을 구하는 제 3 단계 ; 및 상기 제 3 단계에서 구한 차분 방정식(y(n))의 계수(a, b, c)를 최적화하여 새로운 차분 방정식(y'(n))을 구하는 제 4 단계로 이루어지는 고역통과 IIR 필터의 설계 방법. A first step of receiving the threshold frequency W D and the sampling period T and calculating an analog frequency W A ; A second step of converting the system transfer function H (S) in the analog domain into the system transfer function H (Z) in the digital domain by the bilinear transformation method; A third step of obtaining a differential equation y (n) from the system transfer acceptance unit H (Z) in the digital region obtained in the second step; And a fourth step of obtaining a new differential equation y '(n) by optimizing coefficients a, b, c of the differential equation y (n) obtained in the third step Way. 여기서,here, 이다.to be. 디지탈 신호 x(n)를 입력받아 소정시간 지연시키는 지연기(21)와, 지연기(21)의 출력을 MSB 측으로 1비트 시프트하는 시프터(22)와, 지연기(21)의 출력을 소정시간 지연시키는 지연기(23)와, 디지탈 신호 y(n)을 입력받아 소정시간 지연시키는 지연기(24)와, 지연기(24)의 출력을 MSB 측으로 2비트 시프트하는 시프터(25)와, 지연기(24)의 출력을 소정시간 지연시키는 지연기(26)와, 지연기(23)의 출력과 시프터(25)의 출력을 가산하는 가산기(100)와, 가산기(100)의 출력에서 시프터(22)의 출력을 감산하는 감산기(200)와, 디지탈 신호 x(n)와 감산기(200)의 출력을 가산하는 가산기(300)와, 가산기(300)의 출력과 계수 c를 승산하는 승산기(A)와, 지연기(24)의 출력과 지연기(26)의 출력을 가산하는 가산기(400)와, 가산기(400)의 출력과 계수 2t를 승산하는 승산기(B)와, 승산기(A)의 출력에서 승산기(B)의 출력을 감산하는 감산기(500)와, 감산기(500)의 출력과 지연기(26)의 출력을 가산하는 가산기(600)로 구성되는 고역통과 IIR 필터.A shifter 21 for receiving the digital signal x (n) and delaying the digital signal x (n) for a predetermined time, a shifter 22 for shifting the output of the delay unit 21 by one bit toward the MSB, A delay 24 for delaying the digital signal y (n) by a predetermined time, a shifter 25 for shifting the output of the delay 24 by 2 bits toward the MSB, An adder 100 for adding the output of the shifter 23 and the output of the shifter 25 to the output of the adder 100; A multiplier 300 for multiplying the output of the adder 300 by a coefficient c, a subtractor 300 for subtracting the output of the adder 300 from the digital signal x (n) An adder 400 for adding the output of the delay 24 and an output of the delay 26, a multiplier B for multiplying the output of the adder 400 by a coefficient 2t, From output A subtractor 500 for subtracting the output of the multiplier B and an adder 600 for adding the output of the subtractor 500 and the output of the delay 26. The high- 여기서,WD는 임계 주파수, T는 샘플링 시간이다.here, W D is the threshold frequency, and T is the sampling time. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960017472A 1996-05-22 1996-05-22 Design Method of Highpass IIR Filter and Highpass IIR Filter Expired - Fee Related KR0176205B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960017472A KR0176205B1 (en) 1996-05-22 1996-05-22 Design Method of Highpass IIR Filter and Highpass IIR Filter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960017472A KR0176205B1 (en) 1996-05-22 1996-05-22 Design Method of Highpass IIR Filter and Highpass IIR Filter

Publications (2)

Publication Number Publication Date
KR970077985A true KR970077985A (en) 1997-12-12
KR0176205B1 KR0176205B1 (en) 1999-04-01

Family

ID=19459516

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960017472A Expired - Fee Related KR0176205B1 (en) 1996-05-22 1996-05-22 Design Method of Highpass IIR Filter and Highpass IIR Filter

Country Status (1)

Country Link
KR (1) KR0176205B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100585641B1 (en) * 1999-07-12 2006-06-02 엘지전자 주식회사 Infinite Impulse Response Filter Structure

Also Published As

Publication number Publication date
KR0176205B1 (en) 1999-04-01

Similar Documents

Publication Publication Date Title
US4588979A (en) Analog-to-digital converter
EP0227267A2 (en) Digital-to-analog converter
CN1273709A (en) Sample rate converter using polynomial interpolation
JPH082032B2 (en) Correlator for spread spectrum communication
KR970077985A (en) High-pass IIR filter design method and high pass IIR filter
JPS63185232A (en) Adaptive type jitter canceler
KR980006832A (en) Low-pass 11R filter design method and low-pass 11R filter
JP3109389B2 (en) Adaptive filter system
JP3125225B2 (en) Digital / analog converter
US7346639B2 (en) Method and apparatus for suppressing limit cycles in noise shaping filters
JP2583610B2 (en) A / D, D / A converter
JP3041563B2 (en) Finite impulse response filter
JPH02294120A (en) Dc offset elimination circuit for digital signal
JPH07143361A (en) Ringing eliminating device
JP2880580B2 (en) Acyclic digital filter circuit
JPH0662284A (en) Noise removing device
JP3036030B2 (en) Noise shaping type quantizer
KR100251634B1 (en) Apparatus for receiving digital by using polyphase structure
KR970004196B1 (en) Noise deleting apparatus of tv
KR100267251B1 (en) Method and system for minimizing Finite Impulse Response Filter
JP3213957B2 (en) Image signal processing circuit
JPH084214B2 (en) Transversal filter
JP2701501B2 (en) Smoothing device
JPH07202960A (en) Burst waveform generator
KR960008785A (en) Digital noise attenuator

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

FPAY Annual fee payment

Payment date: 20051007

Year of fee payment: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20061113

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20061113

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000