MA36343B1 - Copper metallization process for manufacturing an integrated circuit using wafer level 3d packaging technology - Google Patents

Copper metallization process for manufacturing an integrated circuit using wafer level 3d packaging technology

Info

Publication number
MA36343B1
MA36343B1 MA36343A MA36343A MA36343B1 MA 36343 B1 MA36343 B1 MA 36343B1 MA 36343 A MA36343 A MA 36343A MA 36343 A MA36343 A MA 36343A MA 36343 B1 MA36343 B1 MA 36343B1
Authority
MA
Morocco
Prior art keywords
integrated circuit
wafer level
packaging technology
manufacturing
metallization process
Prior art date
Application number
MA36343A
Other languages
French (fr)
Other versions
MA20150146A1 (en
Inventor
Zahraoui Said
Sbiaa Zouhair
Original Assignee
Nemotek Technologies
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nemotek Technologies filed Critical Nemotek Technologies
Priority to MA36343A priority Critical patent/MA36343B1/en
Priority to PCT/MA2014/000055 priority patent/WO2015147620A1/en
Publication of MA20150146A1 publication Critical patent/MA20150146A1/en
Publication of MA36343B1 publication Critical patent/MA36343B1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H10F39/026—Wafer-level processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/804—Containers or encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses

Landscapes

  • Solid State Image Pick-Up Elements (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Procédé de métallisation 'à base de,cuivre de ligne de connexion (rdl) 32 et de vias traversant 34 (fig .La) destiné à la fabrication d'un circuit intégré en généralet d'un capteur d'image en particulier en utilisant ta technologie wafer level packaging 3d , permettant de réduire le co,ût defabrication et d'avoir une meilleure performance électrique au niveau du dit capteur d'image 1 notamment pour la réalisation des interconnexions dans des circuits intégrés en trois dimensions.Method of metallization 'based on copper connection line (rdl) 32 and through vias 34 (fig .La) for the manufacture of an integrated circuit in general and an image sensor in particular using ta wafer level 3d packaging technology, to reduce the cost of manufacture and to have better electrical performance at said image sensor 1 in particular for the realization of interconnections in three-dimensional integrated circuits.

MA36343A 2013-10-14 2013-10-14 Copper metallization process for manufacturing an integrated circuit using wafer level 3d packaging technology MA36343B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
MA36343A MA36343B1 (en) 2013-10-14 2013-10-14 Copper metallization process for manufacturing an integrated circuit using wafer level 3d packaging technology
PCT/MA2014/000055 WO2015147620A1 (en) 2013-10-14 2014-12-15 Copper metallisation method intended for the production of an integrated circuit using 3d wafer-level packaging technology

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
MA36343A MA36343B1 (en) 2013-10-14 2013-10-14 Copper metallization process for manufacturing an integrated circuit using wafer level 3d packaging technology

Publications (2)

Publication Number Publication Date
MA20150146A1 MA20150146A1 (en) 2015-05-29
MA36343B1 true MA36343B1 (en) 2016-04-29

Family

ID=52589735

Family Applications (1)

Application Number Title Priority Date Filing Date
MA36343A MA36343B1 (en) 2013-10-14 2013-10-14 Copper metallization process for manufacturing an integrated circuit using wafer level 3d packaging technology

Country Status (2)

Country Link
MA (1) MA36343B1 (en)
WO (1) WO2015147620A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10211052B1 (en) * 2017-09-22 2019-02-19 Lam Research Corporation Systems and methods for fabrication of a redistribution layer to avoid etching of the layer
CN113972146B (en) * 2020-07-22 2025-02-18 盛合晶微半导体(江阴)有限公司 Packaging method and semiconductor packaging structure capable of improving gold pad recognition

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10356885B4 (en) * 2003-12-03 2005-11-03 Schott Ag Method of housing components and housed component
EP2135280A2 (en) * 2007-03-05 2009-12-23 Tessera, Inc. Chips having rear contacts connected by through vias to front contacts
KR100889553B1 (en) * 2007-07-23 2009-03-23 주식회사 동부하이텍 System in package and method for fabricating the same
US8710680B2 (en) * 2010-03-26 2014-04-29 Shu-Ming Chang Electronic device package and fabrication method thereof
JP5352534B2 (en) * 2010-05-31 2013-11-27 パナソニック株式会社 Semiconductor device and manufacturing method thereof
JP5810921B2 (en) * 2012-01-06 2015-11-11 凸版印刷株式会社 Manufacturing method of semiconductor device

Also Published As

Publication number Publication date
MA20150146A1 (en) 2015-05-29
WO2015147620A1 (en) 2015-10-01

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