MX9700528A - Configuracion en un procesador de imagenes. - Google Patents

Configuracion en un procesador de imagenes.

Info

Publication number
MX9700528A
MX9700528A MX9700528A MX9700528A MX9700528A MX 9700528 A MX9700528 A MX 9700528A MX 9700528 A MX9700528 A MX 9700528A MX 9700528 A MX9700528 A MX 9700528A MX 9700528 A MX9700528 A MX 9700528A
Authority
MX
Mexico
Prior art keywords
unit block
unit
processor
incrementing
processor element
Prior art date
Application number
MX9700528A
Other languages
English (en)
Other versions
MXPA97000528A (es
Inventor
Robert Forchheimer
Anders Astrom
Original Assignee
Integrated Vision Prod
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Integrated Vision Prod filed Critical Integrated Vision Prod
Publication of MX9700528A publication Critical patent/MX9700528A/es
Publication of MXPA97000528A publication Critical patent/MXPA97000528A/es

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00General purpose image data processing
    • G06T1/20Processor architectures; Processor configuration, e.g. pipelining
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/80Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8015One dimensional arrays, e.g. rings, linear arrays, buses

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Image Processing (AREA)
  • Logic Circuits (AREA)
  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
  • Ultra Sonic Daignosis Equipment (AREA)
  • Processing Or Creating Images (AREA)
  • Measuring And Recording Apparatus For Diagnosis (AREA)
  • Manufacture Or Reproduction Of Printing Formes (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)

Abstract

La presente invencion se refiere a un procesador paralelo que contiene un numero de elementos procesadores del mismo tipo, que se integran sobre uno y el mismo chip semiconductor. El procesador es del tipo que permite el procesamiento de imágenes y de señales de la informacion almacenada en el elemento procesador. El dispositivo contiene un bloque unitario (3) para cada elemento procesador, y se caracteriza porque cada bloque unitario comprende cuando menos dos unidades incrementadoras (1a, 1b) que están diseñadas para sumar una unidad suministrada al bloque unitario, y una señal que se origina desde una unidad incrementadora correspondiente a la unidad respectiva en el bloque unitario precedente más cercano en todas las direcciones de la matriz del elemento procesador. Cada bloque unitario (3) contiene además cuando menos una unidad logica (2) que está diseñada para realizar operaciones logicas Booleanas sobre las señales recibidas desde las unidades incrementadoras del bloque unitario. La figura más representativa de la invencion es la numero 1.
MXPA/A/1997/000528A 1994-07-22 1997-01-20 Configuracion en un procesador de imagenes MXPA97000528A (es)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
SE9402551-7 1994-07-22
SE9402551A SE9402551L (sv) 1994-07-22 1994-07-22 Anordning vid en bildbehandlingsprocessor
PCT/SE1995/000868 WO1996003700A1 (en) 1994-07-22 1995-07-18 Arrangement at an image processor

Publications (2)

Publication Number Publication Date
MX9700528A true MX9700528A (es) 1998-05-31
MXPA97000528A MXPA97000528A (es) 1998-10-23

Family

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Also Published As

Publication number Publication date
WO1996003700A1 (en) 1996-02-08
SE502485C2 (sv) 1995-10-30
DE69515311T2 (de) 2000-10-19
US5982393A (en) 1999-11-09
DE69515311D1 (de) 2000-04-06
JP2000509170A (ja) 2000-07-18
BR9508422A (pt) 1997-11-18
CN1098494C (zh) 2003-01-08
EP0772835B1 (en) 2000-03-01
EP0772835A1 (en) 1997-05-14
AU685311B2 (en) 1998-01-15
AU3090195A (en) 1996-02-22
CN1152966A (zh) 1997-06-25
SE9402551L (sv) 1995-10-30
CA2195674A1 (en) 1996-02-08
ATE190152T1 (de) 2000-03-15
SE9402551D0 (sv) 1994-07-22

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Legal Events

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