NO20053531L - Flernivaminnecelle med laterale flytende udopede mellomsjiktstrukturer - Google Patents

Flernivaminnecelle med laterale flytende udopede mellomsjiktstrukturer

Info

Publication number
NO20053531L
NO20053531L NO20053531A NO20053531A NO20053531L NO 20053531 L NO20053531 L NO 20053531L NO 20053531 A NO20053531 A NO 20053531A NO 20053531 A NO20053531 A NO 20053531A NO 20053531 L NO20053531 L NO 20053531L
Authority
NO
Norway
Prior art keywords
layer structures
memory transistor
memory cell
intermediate layer
level memory
Prior art date
Application number
NO20053531A
Other languages
English (en)
Inventor
Bohumil Lojek
Original Assignee
Atmel Corp A Delaware Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp A Delaware Corp filed Critical Atmel Corp A Delaware Corp
Publication of NO20053531L publication Critical patent/NO20053531L/no

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/687—Floating-gate IGFETs having more than two programming levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H10D30/6893—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode wherein the floating gate has multiple non-connected parts, e.g. multi-particle floating gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

En flernivå ikke-volatil minnetransistor (33) blir dannet i et halvledersubstrat (57). En ledende polysilisium styringsport (51, 62) som har motsatte sidevegger er isolert i en avstand (56) like over substratet. De ledende polysilisium udopede mellomsjiktstrukturerer (53, 55, 91, 93) er skilt fra motstående sidevegger av et tynt tunneloksidlag (59, 74). Kilde- og drensimplantater (61, 63, 101, 103) er under eller noe utenfor de udopede mellomsjiktstrukturerer. Isolasjonsmaterialet (104,109) blir plassert over strukturen med et hull (125) kuttet over kontrollportelektroden for kontakt med en portelektrode (127) forbundet til denne eller en del av en ledende ordlinje. Tilleggslavspennings-transistorer, (23-26) som kan bli laget samtidig som dannelsen av minnetransistoren, påfører motsatte faseklokkepulser ((l,p2) til kilde- og drenselektrode slik at den første ene side av minnetransistoren kan bli skrevet til eller lest til og så til den andre side.
NO20053531A 2002-12-20 2005-07-19 Flernivaminnecelle med laterale flytende udopede mellomsjiktstrukturer NO20053531L (no)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/327,336 US6831325B2 (en) 2002-12-20 2002-12-20 Multi-level memory cell with lateral floating spacers
PCT/US2003/040205 WO2004059737A1 (en) 2002-12-20 2003-12-18 Multi-level memory cell with lateral floating spacers

Publications (1)

Publication Number Publication Date
NO20053531L true NO20053531L (no) 2005-07-19

Family

ID=32594228

Family Applications (1)

Application Number Title Priority Date Filing Date
NO20053531A NO20053531L (no) 2002-12-20 2005-07-19 Flernivaminnecelle med laterale flytende udopede mellomsjiktstrukturer

Country Status (10)

Country Link
US (3) US6831325B2 (no)
EP (1) EP1576668A4 (no)
JP (1) JP2006511940A (no)
KR (1) KR20050084343A (no)
CN (1) CN100364098C (no)
AU (1) AU2003300994A1 (no)
CA (1) CA2508810A1 (no)
NO (1) NO20053531L (no)
TW (1) TW200427066A (no)
WO (1) WO2004059737A1 (no)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6888192B2 (en) * 2003-04-25 2005-05-03 Atmel Corporation Mirror image non-volatile memory cell transistor pairs with single poly layer
TW594944B (en) * 2003-06-05 2004-06-21 Taiwan Semiconductor Mfg Method of forming an embedded flash memory device
US7072210B2 (en) * 2004-04-26 2006-07-04 Applied Intellectual Properties Co., Ltd. Memory array
US7457154B2 (en) * 2004-03-15 2008-11-25 Applied Intellectual Properties Co., Ltd. High density memory array system
US8099783B2 (en) * 2005-05-06 2012-01-17 Atmel Corporation Security method for data protection
US7622349B2 (en) * 2005-12-14 2009-11-24 Freescale Semiconductor, Inc. Floating gate non-volatile memory and method thereof
KR100660284B1 (ko) * 2005-12-28 2006-12-20 동부일렉트로닉스 주식회사 스플리트 게이트 구조를 가지는 비휘발성 기억 소자 및 그제조 방법
US7439567B2 (en) * 2006-08-09 2008-10-21 Atmel Corporation Contactless nonvolatile memory array
KR100748003B1 (ko) * 2006-08-31 2007-08-08 동부일렉트로닉스 주식회사 임베디드 비휘발성 메모리 및 그 제조방법
US7714376B2 (en) 2006-12-19 2010-05-11 Taiwan Semiconductor Manufacturing Co., Ltd. Non-volatile memory device with polysilicon spacer and method of forming the same
TW200847446A (en) * 2007-05-16 2008-12-01 Nanya Technology Corp Two-bit flash memory cell and method for manufacturing the same
CN101465161A (zh) * 2008-12-30 2009-06-24 上海宏力半导体制造有限公司 共享字线的分栅式闪存
DE102010002455B4 (de) 2010-02-26 2017-06-01 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Nichtflüchtiger Speichertransistor und Verfahren zu dessen Herstellung
US8791522B2 (en) * 2011-10-12 2014-07-29 Macronix International Co., Ltd. Non-volatile memory
US8575683B1 (en) * 2012-05-16 2013-11-05 United Microelectronics Corp. Semiconductor device and method of fabricating the same
KR102074942B1 (ko) 2013-07-29 2020-02-10 삼성전자 주식회사 비휘발성 메모리 트랜지스터 및 이를 포함하는 소자
CN109817624B (zh) * 2019-01-22 2020-09-25 上海华虹宏力半导体制造有限公司 存储器及其操作方法
CN111540739B (zh) * 2020-05-13 2022-08-19 复旦大学 一种基于双隧穿晶体管的半浮栅存储器及其制备方法

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4833096A (en) 1988-01-19 1989-05-23 Atmel Corporation EEPROM fabrication process
JP2504599B2 (ja) * 1990-02-23 1996-06-05 株式会社東芝 不揮発性半導体記憶装置
US5021848A (en) 1990-03-13 1991-06-04 Chiu Te Long Electrically-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area and the method of fabricating thereof
JPH0485883A (ja) * 1990-07-26 1992-03-18 Fujitsu Ltd 不揮発性半導体記憶装置及びその製造方法
US5618742A (en) 1992-01-22 1997-04-08 Macronix Internatioal, Ltd. Method of making flash EPROM with conductive sidewall spacer contacting floating gate
US5477068A (en) 1992-03-18 1995-12-19 Rohm Co., Ltd. Nonvolatile semiconductor memory device
US5640031A (en) 1993-09-30 1997-06-17 Keshtbod; Parviz Spacer flash cell process
US5479368A (en) 1993-09-30 1995-12-26 Cirrus Logic, Inc. Spacer flash cell device with vertically oriented floating gate
FR2718289B1 (fr) * 1994-03-30 1996-08-02 Sgs Thomson Microelectronics Cellule mémoire électriquement programmable.
KR0151621B1 (ko) * 1994-11-05 1998-10-01 문정환 비휘발성 메모리 반도체 소자 및 이의 제조방법
JP3403877B2 (ja) 1995-10-25 2003-05-06 三菱電機株式会社 半導体記憶装置とその製造方法
JP2910647B2 (ja) * 1995-12-18 1999-06-23 日本電気株式会社 不揮発性半導体記憶装置の製造方法
US5760435A (en) * 1996-04-22 1998-06-02 Chartered Semiconductor Manufacturing, Ltd. Use of spacers as floating gates in EEPROM with doubled storage efficiency
DE19638969C2 (de) 1996-09-23 2002-05-16 Mosel Vitelic Inc EEPROM mit einem Polydistanz-Floating-Gate und Verfahren zu deren Herstellung
US5963806A (en) 1996-12-09 1999-10-05 Mosel Vitelic, Inc. Method of forming memory cell with built-in erasure feature
KR100206985B1 (ko) * 1997-03-14 1999-07-01 구본준 플래시 메모리 소자 및 그 제조방법
JP3183396B2 (ja) 1997-11-20 2001-07-09 日本電気株式会社 不揮発性半導体記憶装置およびその製造方法
JPH11186416A (ja) * 1997-12-19 1999-07-09 Rohm Co Ltd 不揮発性半導体記憶装置およびその製造方法
US5972752A (en) 1997-12-29 1999-10-26 United Semiconductor Corp. Method of manufacturing a flash memory cell having a tunnel oxide with a long narrow top profile
US6091101A (en) * 1998-03-30 2000-07-18 Worldwide Semiconductor Manufacturing Corporation Multi-level flash memory using triple well
US6243289B1 (en) * 1998-04-08 2001-06-05 Micron Technology Inc. Dual floating gate programmable read only memory cell structure and method for its fabrication and operation
US6043530A (en) * 1998-04-15 2000-03-28 Chang; Ming-Bing Flash EEPROM device employing polysilicon sidewall spacer as an erase gate
US6074914A (en) * 1998-10-30 2000-06-13 Halo Lsi Design & Device Technology, Inc. Integration method for sidewall split gate flash transistor
JP4058219B2 (ja) * 1999-09-17 2008-03-05 株式会社ルネサステクノロジ 半導体集積回路
US6501680B1 (en) * 1999-10-07 2002-12-31 Hyundai Electronics Industries Co., Ltd. Nonvolatile memory, cell array thereof, and method for sensing data therefrom
US6255689B1 (en) * 1999-12-20 2001-07-03 United Microelectronics Corp. Flash memory structure and method of manufacture
JP2002050703A (ja) * 2000-08-01 2002-02-15 Hitachi Ltd 多値不揮発性半導体記憶装置
KR100375220B1 (ko) * 2000-10-12 2003-03-07 삼성전자주식회사 플래시 메모리 장치 형성방법
US6624029B2 (en) * 2000-11-30 2003-09-23 Atmel Corporation Method of fabricating a self-aligned non-volatile memory cell
US6479351B1 (en) 2000-11-30 2002-11-12 Atmel Corporation Method of fabricating a self-aligned non-volatile memory cell
US6919242B2 (en) * 2003-04-25 2005-07-19 Atmel Corporation Mirror image memory cell transistor pairs featuring poly floating spacers
US7098106B2 (en) * 2004-07-01 2006-08-29 Atmel Corporation Method of making mirror image memory cell transistor pairs featuring poly floating spacers

Also Published As

Publication number Publication date
CN1729573A (zh) 2006-02-01
US20040119112A1 (en) 2004-06-24
EP1576668A4 (en) 2008-03-26
KR20050084343A (ko) 2005-08-26
AU2003300994A1 (en) 2004-07-22
CA2508810A1 (en) 2004-07-15
TW200427066A (en) 2004-12-01
US7180126B2 (en) 2007-02-20
CN100364098C (zh) 2008-01-23
EP1576668A1 (en) 2005-09-21
US20050062092A1 (en) 2005-03-24
US20070134875A1 (en) 2007-06-14
WO2004059737B1 (en) 2004-09-02
US6831325B2 (en) 2004-12-14
JP2006511940A (ja) 2006-04-06
WO2004059737A1 (en) 2004-07-15

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