NO990075L - Storage cell with floating port and reduced charge leakage - Google Patents

Storage cell with floating port and reduced charge leakage

Info

Publication number
NO990075L
NO990075L NO990075A NO990075A NO990075L NO 990075 L NO990075 L NO 990075L NO 990075 A NO990075 A NO 990075A NO 990075 A NO990075 A NO 990075A NO 990075 L NO990075 L NO 990075L
Authority
NO
Norway
Prior art keywords
storage cell
charge leakage
floating port
reduced charge
floating
Prior art date
Application number
NO990075A
Other languages
Norwegian (no)
Other versions
NO990075D0 (en
Inventor
Bradley J Larsen
Tsung-Ching Wu
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Publication of NO990075D0 publication Critical patent/NO990075D0/en
Publication of NO990075L publication Critical patent/NO990075L/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/46—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with an inter-gate dielectric layer also being used as part of the peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

En prosess for å fabrikkere en lagercelle med flytende port (60) med redusert ladningslekkasje. En oksid re-vekst (73) dannes over sidene av den flytende port (69) og dekkes så med et oksidbeskyttende dekke (64, 66). Strukturen er anvendelig for salisid og ikke-salisid lagerceller og er spesielt nyttig i lagerceller med flytende port med portstabler som har abnormt formede sidevegger.A process for fabricating a floating port storage cell (60) with reduced charge leakage. An oxide re-growth (73) is formed over the sides of the floating port (69) and is then covered with an oxide protective cover (64, 66). The structure is applicable to salicide and non-salicide storage cells and is particularly useful in floating gate storage cells with gate stacks having abnormally shaped side walls.

NO990075A 1997-05-09 1999-01-08 Storage cell with floating port and reduced charge leakage NO990075L (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US85369197A 1997-05-09 1997-05-09
PCT/US1998/008709 WO1998050960A1 (en) 1997-05-09 1998-04-30 Floating gate memory cell with charge leakage prevention

Publications (2)

Publication Number Publication Date
NO990075D0 NO990075D0 (en) 1999-01-08
NO990075L true NO990075L (en) 1999-03-08

Family

ID=25316673

Family Applications (1)

Application Number Title Priority Date Filing Date
NO990075A NO990075L (en) 1997-05-09 1999-01-08 Storage cell with floating port and reduced charge leakage

Country Status (7)

Country Link
EP (1) EP0934603A1 (en)
JP (1) JP2000513879A (en)
KR (1) KR20000023619A (en)
CN (1) CN1227001A (en)
CA (1) CA2259631A1 (en)
NO (1) NO990075L (en)
WO (1) WO1998050960A1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6417046B1 (en) * 2000-05-05 2002-07-09 Taiwan Semiconductor Manufacturing Company Modified nitride spacer for solving charge retention issue in floating gate memory cell
KR100395755B1 (en) * 2001-06-28 2003-08-21 삼성전자주식회사 Non-volatile memory device and method of fabricating the same
CN100481516C (en) * 2002-12-27 2009-04-22 夏普株式会社 Semiconductor storage and portable electronic device
CN100382317C (en) * 2003-12-19 2008-04-16 应用智慧有限公司 spacer trapped memory
KR100634167B1 (en) 2004-02-06 2006-10-16 삼성전자주식회사 Semiconductor device and manufacturing method thereof
KR100699830B1 (en) * 2004-12-16 2007-03-27 삼성전자주식회사 Non-volatile memory device and method for improving erase efficiency
JP4974880B2 (en) * 2005-01-27 2012-07-11 スパンション エルエルシー Semiconductor device and manufacturing method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5479018A (en) * 1989-05-08 1995-12-26 Westinghouse Electric Corp. Back surface illuminated infrared detector
US5424567A (en) * 1991-05-15 1995-06-13 North American Philips Corporation Protected programmable transistor with reduced parasitic capacitances and method of fabrication

Also Published As

Publication number Publication date
EP0934603A1 (en) 1999-08-11
CA2259631A1 (en) 1998-11-12
NO990075D0 (en) 1999-01-08
WO1998050960A1 (en) 1998-11-12
JP2000513879A (en) 2000-10-17
KR20000023619A (en) 2000-04-25
CN1227001A (en) 1999-08-25

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Legal Events

Date Code Title Description
FC2A Withdrawal, rejection or dismissal of laid open patent application