PL157889B1 - Unmasked interrupt handling address changing circuit for z80 microprocessor or its equivalent - Google Patents

Abstract

System of address change of non-maskable interrupt for an 8-byte microprocessor, being an additional system collaborating with the address bus, data bus and microprocessor control bus and also with operational memory data bus, characterised in that it comprises a information fetch cycle detection module (BWCPR), information code generation module (BGKR) and operational memory interlock module (BBP), at the same time subsequent inputs, from (IAO) to (IA15) of the information fetch cycle detection module (BWCPR) being connected with respective address lines, from (AO) to (A15) of the address line, and (IM1) input of this module being connected with the microprocessor information fetch cycle line mode (-M1), whereas the module output (RESTART) is connected simultaneously with the operational memory interlock module (BBP) input (IBP) and input of information code generating module (BGKR), whereas outputs of information code generating module, from (OD3) to (OD5), are connected with respective lines, (D3) to (D5), of data bus (DB), the lines of which, from (D0) to (D7), are connected respectively with outputs (OP0) to (OP7) of the operation memory interlock module (BBP), inputs of which, from (IPO) to (IP7), are connected respectively with data lines from (DP0) to (DP7) of the operational memory module.<IMAGE>

Description

REPUBLIC

POLAND

Polish Republic

Application number: 269087

Date of notification: November 27, 1987

PATENT DESCRIPTION® PL® 157889 @ BI

®) IntCl ⁵ :

G06F 12/02 G11C 8/00

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GENERAL

A circuit for changing the address of a nonmaskable interrupt handler for an eight-bit microprocessor

Application announced:

May 30, 1989 BUP 11/89

The holder of the patent: Poznań University of Technology, Poznań, PL

Inventor:

Bronisław Bilewski, Poznań, PL

The grant of the patent was announced on: 07/31/1992 WUP 07/92

PL 157889 BI

A circuit for changing the address of a non-maskable interrupt service for an eight-bit microprocessor, which is an additional circuit cooperating with the address, data and control bus of the microcomputer and with the operating memory data bus, characterized by the fact that it consists of an instruction fetch cycle detection block (BWCPR), an instruction code generation block ( BGKR) and the main memory blocking block (BBP), the successive inputs (IAO) to (1A15) of the command fetch cycle detection (BWCPR) block are sequentially connected to the address lines (AO) to (A15) of the address bus, respectively, and the input (IM1) of this block is connected to the microprocessor fetch cycle status line (-M1), and the RESTART output of this block is connected simultaneously to the blocking input (IBP) of the main memory block (BBP) and to the input of the order code generation block ( BGKR), while the outputs (OD3) to (OD5) of the order code generation block (BGKR) are connected to lines (D3) to (D5) of the data bus (DB), respectively and (DO) to (D7) are connected respectively to the outputs (OPO) to (OP7) of the operating memory blocking block (BBP), whose inputs (IPO) to (IP7) are connected to data lines (DPO) to (DP7) respectively working memory.

ARRANGEMENT OF THE NONMASKABLE INTERRUPT SERVICE ADDRESS FOR THE OCTOBITOR MICROPROCESSOR

Claims (1)

Patent claim A circuit for changing the address of a non-maskable interrupt service for an eight-bit microprocessor, which is an additional circuit cooperating with the address, data and control bus of the micrtktmppUera and also with the temperature memory data bus, characterized by the fact that it consists of the command fetch cycle detection block / BrCPR /, the command generation block / BGKR / and temperature blocking block / BBP /, the subsequent inputs / IAO / to / IA15 / command download cycle detection / BWCPR / are sequentially connected to address lines, respectively / AO / to / A15 / address bus, and the input / M1 / of this block is connected to the / -Ml / milu-processor command cycle status line, and the / RESTART / output of this block is connected Simultaneously with the blocking input / IBP / working memory blocking block / B3P / also with the input of the code generation block of the command / BGIK ^ R, while the outputs / 003 / to / 0D5 / of the command code generation block / BGKR / are connected with the lines Z> 3 / to / D5 / data bus / 03 /, respectively no / 00 / dt / D7l are connected, respectively, dt outputs / GPOi to / 0P7 / blocking memory block / BBP /, whose inputs / IPO / to / IP7 / are connected to the data lines / DPO / to / DP7 / operating memory, respectively . The subject of the invention is a system for changing the address of an interrupt service of a non-maskable eight-bit microprocessor, in particular the Z80 microprocessor or the Jegt tdpc, for application, especially in microcomputer systems with a Z80 microprocessor, in which the memory cell with the address 66H is used for data storage, not a program. The eight bit microprocessor, especially the Z80, has an input for a non-masked interrupt request. When this interrupt is reported, the microprocessor automatically proceeds to execute the program starting in the main memory location with the address 56H. In known microcomputer systems based on the Z80 rmcroprocessor, a non-mascot interrupt is used, which memories with addresses 66H, 67H and 68H contain the start of an interrupt handler or a jump command dt of this program. In turn, in microcomputers with the Z80 microprocessor, working under the control of the CP / M operating system, the memory area containing the cell with the address 66H is intended for data retrieval. For this reason, the cell with the address 66H cannot contain the instruction required for the correct handling of the nonmaskable interrupt. Therefore, in the case of these shortcuts containing an eight-bit microprocessor, especially the Z80, and running under the CF / M operating system, a non-maskable interrupt cannot be used. The circuit for changing the address of a non-maskable interrupt service for an eight-bit microprocessor according to the invention, which is an additional circuit cooperating with the address, data and control bus of the microcomputer and with the data bus of the operating memory, is characterized by the fact that it consists of a block detection cycle of an instruction fetch, an instruction generation block and a block. blocking the operating memory, the inputs of the command fetch cycle detection block are connected sequentially with adress lines, and the input of this block is connected with the state line of the microprocessor instruction fetch cycle, At the same time, the output of the instruction fetch cycle detection block is connected simultaneously with the blocking input of the operating memory blocking block. together with the input of the command generation block, with the input The outputs of the latching memory block are connected to the main memory data lines, respectively, and the outputs of the main memory block are connected to the microprocessor data bus lines, respectively, while the command code generation block outputs are connected to the microprocessor data bus lines, respectively. The instruction fetch cycle detection block analyzes the state of the address lines and the instruction fetch cycle status lines and activates its output when it detects the state corresponding to fetching the instruction from the cell. In turn, the memory locking block, in the case of an active state of the input line, locks the memory output circuit in such a way that it does not drive the microprocessor data line. The command code generation block, in the case of the active state of the input line, controls its outputs connected to the microprocessor data line, setting on them the command code What microprocessor pcbie will in this cycle. The task of the generated command code is to change the state of the counter count <w to the address where the beginning of the nonmaskable interrupt handler is placed. The subject of the invention is explained in more detail on the example of an embodiment with a Z80 microprocessor, shown in the drawing, which shows a block diagram of the system, with a schematic presentation of external and internal connections of individual blocks. The system cooperates with the bus: address, data and control of the microprocessor and with the data bus of the operating memory. The system consists of the BWCFR instruction fetch cycle detection block, BGKR instruction code generation block and BBP main memory locking block, The inputs IAO to IA15 of the BWCPR instruction fetch cycle detection block are connected sequentially to the address lines, AO and A15 of the address bus, respectively, and the input IM1 of this block is connected to the status line of the download cycle of the instruction -M1 of microprocessor Z80. The RESTART output of the BWCPR block is simultaneously connected to the blocking input of the IBP of the blocking of the BBP operating memory and to the input of the instruction code generation block BGKR. The inputs IPO to IP7 of the blocking block of the BBP are connected to the data lines of the main memory DPO, respectively. The outputs 0F0 to 0P7 of the BBF are connected to lines DO through D7 of the microprocessor's CD bus, respectively. The outputs 0D3 to 0D5 of the BGKR instruction code generation block are connected to lines D3 to D5 of the DB, respectively. System operation is as follows. The PROM type Κ565ΚΓ5, marked as U1 in the figure, decodes the state of address lines A10 to A15, activating the Q5 input (signal -IAH) when the state of all these lines is defined with a logical value of 0. In turn, the PROM type K565RT5, marked on in the figure as U2, it decodes the state of the address lines AO to A8, activating the output Q6 (signal -IAL) in a situation when the inputs are logical values from dc to address 66H. The output signals of both PROM circuits (-IAH and -IAL), the address line A9 and the Union -M1 are connected to the inputs AO to A3 of the 74LS85 comparator system. The inputs BO to B3 cor ^^ are in the state defined by the logical value 0. Due to this connection, the output A = B (RESTART signal) is in the active state during the instruction download cycle from the memory location with the address 66H. In turn, the blocking of the BBP memory, in the case of the active state of the RESTART line, locks the RAM output register. As a result, the output register does not drive the microprocessor data line. The BGKR instruction code generation block includes three gates 7406 with open collector outputs. The RESTART signal is supplied to the outputs of these gates and if it has a logical value of 1, the lines D3, D4 and D5 of the microprocessor data bus are activated, depending on the state of the jumpers Z1 to Z3. The remaining lines of the data bus are in a state defined by a logical value of 1. This state of the data bus is equivalent to the generation of the RST restart command code by the BGKR block with a number depending on the state from Z1 to Z3. In the booster of the restart command execution, the microprocessor instruction counter changes to the address at which the beginning of the nonmaskable interrupt handler is written. The use of the system according to the invention allows the use of non-maskable interrupts in microprocessors with an eight-bit microprocessor, especially Z80 and work4 157 889 operating system CF / M or Other operating system <W compatible operating system