PL359838A1 - Sposób wytwarzania nano-ścieżek - Google Patents
Sposób wytwarzania nano-ścieżekInfo
- Publication number
- PL359838A1 PL359838A1 PL03359838A PL35983803A PL359838A1 PL 359838 A1 PL359838 A1 PL 359838A1 PL 03359838 A PL03359838 A PL 03359838A PL 35983803 A PL35983803 A PL 35983803A PL 359838 A1 PL359838 A1 PL 359838A1
- Authority
- PL
- Poland
- Prior art keywords
- paths
- producing nano
- nano
- producing
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
- H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
- H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
- H10P50/696—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
- H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
- H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
- H10P50/695—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
- H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
- H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
- H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
- H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
- H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
- H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
- H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
- H10P76/4088—Processes for improving the resolution of the masks
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PL359838A PL204687B1 (pl) | 2003-04-24 | 2003-04-24 | Sposób wytwarzania nano-ścieżek |
| EP04460012A EP1473760A3 (en) | 2003-04-24 | 2004-04-23 | Technique for nano-lines fabrication |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PL359838A PL204687B1 (pl) | 2003-04-24 | 2003-04-24 | Sposób wytwarzania nano-ścieżek |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| PL359838A1 true PL359838A1 (pl) | 2004-11-02 |
| PL204687B1 PL204687B1 (pl) | 2010-02-26 |
Family
ID=32986094
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PL359838A PL204687B1 (pl) | 2003-04-24 | 2003-04-24 | Sposób wytwarzania nano-ścieżek |
Country Status (2)
| Country | Link |
|---|---|
| EP (1) | EP1473760A3 (pl) |
| PL (1) | PL204687B1 (pl) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1527894A (en) * | 1975-10-15 | 1978-10-11 | Mullard Ltd | Methods of manufacturing electronic devices |
| NL188432C (nl) * | 1980-12-26 | 1992-06-16 | Nippon Telegraph & Telephone | Werkwijze voor het vervaardigen van een mosfet. |
| JP3462485B2 (ja) * | 2001-07-19 | 2003-11-05 | 株式会社半導体先端テクノロジーズ | 微細レジストパターンの形成方法 |
-
2003
- 2003-04-24 PL PL359838A patent/PL204687B1/pl unknown
-
2004
- 2004-04-23 EP EP04460012A patent/EP1473760A3/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| PL204687B1 (pl) | 2010-02-26 |
| EP1473760A2 (en) | 2004-11-03 |
| EP1473760A3 (en) | 2006-03-29 |
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