PL445769A1 - Bistable flip-flop - Google Patents

Bistable flip-flop

Info

Publication number
PL445769A1
PL445769A1 PL445769A PL44576923A PL445769A1 PL 445769 A1 PL445769 A1 PL 445769A1 PL 445769 A PL445769 A PL 445769A PL 44576923 A PL44576923 A PL 44576923A PL 445769 A1 PL445769 A1 PL 445769A1
Authority
PL
Poland
Prior art keywords
transistors
pair
drains
pairs
transistor
Prior art date
Application number
PL445769A
Other languages
Polish (pl)
Other versions
PL248470B1 (en
Inventor
Piotr Z. Wieczorek
Krzysztof Gołofit
Original Assignee
Talkin Things Spółka Akcyjna
Politechnika Warszawska
Amorphic Technologies Spółka Z Ograniczoną Odpowiedzialnością
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Talkin Things Spółka Akcyjna, Politechnika Warszawska, Amorphic Technologies Spółka Z Ograniczoną Odpowiedzialnością filed Critical Talkin Things Spółka Akcyjna
Priority to PL445769A priority Critical patent/PL248470B1/en
Publication of PL445769A1 publication Critical patent/PL445769A1/en
Priority to PCT/IB2024/057516 priority patent/WO2025032464A1/en
Publication of PL248470B1 publication Critical patent/PL248470B1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0233—Bistable circuits
    • H03K3/02332—Bistable circuits of the primary-secondary type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0233—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3562—Bistable circuits of the primary-secondary type

Landscapes

  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

Przerzutnik bistabilny posiada dwie pary tranzystorów (T2, T3), (T7, T8), których dreny dołączone są do zacisku zasilającego (HRV) poprzez rezystory (R1, R2, R3, R4). W parach tych tranzystory są połączone ze sobą źródłami i dołączone są do masy układu (gnd), a każda bramka tranzystora dołączona jest do drenu drugiego tranzystora w danej parze. Przerzutnik posiada kolejne dwie pary tranzystorów (T1, T4), (T6, T9), gdzie tranzystory w parach są połączone ze sobą źródłami (T1, T4), (T6, T9), a połączone źródła są dołączone do masy układu (gnd) poprzez tranzystory zegarowe (T5), (T10). Bramki tranzystorów zegarowych (T5), (T10) dołączone są do zacisków wejściowych: niezanegowanego (CLK) i zanegowanego (nCLK). Dreny tranzystorów trzeciej i czwartej pary (T1, T4), (T6, T9) dołączone są kolejno do drenów tranzystorów pierwszej i drugiej pary (T2, T3), (T7, T8). Natomiast bramki tranzystorów trzeciej pary (T1, T4) dołączone są kolejno do drenów tranzystorów czwartej pary (T6, T9), podczas gdy bramki tranzystorów czwartej pary (T6, T9) dołączone są w odwrotnej kolejności do drenów tranzystorów trzeciej pary (T1, T4). Zaciski wyjściowe niezanegowany (Q) i zanegowany (nQ) dołączone są kolejno do drenów drugiego tranzystora czwartej pary (T9) i pierwszego tranzystora czwartej pary (T6). Ponadto, do drenu drugiego tranzystora zegarowego (T10) dołączony jest zacisk wstrzykiwania ładunku (CI).The bistable flip-flop has two pairs of transistors (T2, T3), (T7, T8), the drains of which are connected to the power terminal (HRV) through resistors (R1, R2, R3, R4). In these pairs, the transistors are connected to each other by sources and connected to the system ground (gnd), and each transistor gate is connected to the drain of the second transistor in a given pair. The flip-flop has two more pairs of transistors (T1, T4), (T6, T9), where the transistors in pairs are connected to each other with sources (T1, T4), (T6, T9), and the connected sources are connected to the system ground (gnd). via clock transistors (T5), (T10). The gates of the clock transistors (T5), (T10) are connected to the input terminals: uninverted (CLK) and inverted (nCLK). The drains of the third and fourth pairs of transistors (T1, T4), (T6, T9) are connected to the drains of the first and second pair of transistors (T2, T3), (T7, T8). However, the gates of the third pair of transistors (T1, T4) are connected sequentially to the drains of the fourth pair of transistors (T6, T9), while the gates of the fourth pair of transistors (T6, T9) are connected in the reverse order to the drains of the third pair of transistors (T1, T4). . The unnegated (Q) and negated (nQ) output terminals are connected to the drains of the second transistor of the fourth pair (T9) and the first transistor of the fourth pair (T6). Additionally, a charge injection (CI) terminal is connected to the drain of the second clock transistor (T10).

PL445769A 2023-08-05 2023-08-05 Bistable flip-flop PL248470B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PL445769A PL248470B1 (en) 2023-08-05 2023-08-05 Bistable flip-flop
PCT/IB2024/057516 WO2025032464A1 (en) 2023-08-05 2024-08-02 Rfid carrier frequency divider and bistable

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PL445769A PL248470B1 (en) 2023-08-05 2023-08-05 Bistable flip-flop

Publications (2)

Publication Number Publication Date
PL445769A1 true PL445769A1 (en) 2024-01-15
PL248470B1 PL248470B1 (en) 2025-12-15

Family

ID=89543791

Family Applications (1)

Application Number Title Priority Date Filing Date
PL445769A PL248470B1 (en) 2023-08-05 2023-08-05 Bistable flip-flop

Country Status (1)

Country Link
PL (1) PL248470B1 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0730381A (en) * 1993-06-24 1995-01-31 Toshiba Corp Master-slave flip-flop
DE102004009283A1 (en) * 2004-02-26 2005-09-22 Infineon Technologies Ag Flip-flop circuit and method for processing a signal

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0730381A (en) * 1993-06-24 1995-01-31 Toshiba Corp Master-slave flip-flop
DE102004009283A1 (en) * 2004-02-26 2005-09-22 Infineon Technologies Ag Flip-flop circuit and method for processing a signal

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
T. MEISTER, K. ISHIDA, A. SOU, C. CARTA AND F. ELLINGER: "IEEE Solid-State Circuits Letters, vol. 3, pp. 134-137, 2020", 3.93-MHZ/328-ΜW DYNAMIC FREQUENCY DIVIDER IN FLEXIBLE A-IGZO TFT TECHNOLOGY, *

Also Published As

Publication number Publication date
PL248470B1 (en) 2025-12-15

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