PL248470B1 - Bistable flip-flop - Google Patents

Abstract

The flip-flop has two pairs of transistors (T2, T3), (T7, T8), whose drains are connected to the supply terminal (HRV) via resistors (R1, R2, R3, R4). In these pairs, the transistors are connected to each other through their sources and connected to the circuit ground (GND), and each transistor's gate is connected to the drain of the other transistor in the pair. The flip-flop has two further pairs of transistors (T1, T4), (T6, T9), where the transistors in the pairs are connected to each other through their sources (T1, T4), (T6, T9), and the combined sources are connected to the circuit ground (GND) via clock transistors (T5), (T10). The gates of clock transistors (T5), (T10) are connected to the non-inverted (CLK) and inverted (nCLK) input terminals. The drains of transistors in the third and fourth pairs (T1, T4), (T6, T9), and (T7, T8) are connected sequentially to the drains of transistors in the first and second pairs (T2, T3), and (T7, T8). The gates of the third pair (T1, T4) are connected sequentially to the drains of transistors in the fourth pair (T6, T9), while the gates of the fourth pair (T6, T9) are connected in reverse order to the drains of transistors in the third pair (T1, T4). The unnegated (Q) and negated (nQ) output terminals are connected sequentially to the drains of the second transistor in the fourth pair (T9) and the first transistor in the fourth pair (T6). In addition, the charge injection (CI) terminal is connected to the drain of the second clock transistor (T10).

Description

Description of the invention

The subject of the invention is a master-slave type bistable flip-flop, especially for frequency dividers used in NFC RFID tags.

German invention DE102004009283A1 describes a master-slave bistable flip-flop in which the inversion between the master and slave blocks (1, 2) is not achieved by switching the corresponding current sources on and off in the real sense, but rather by applying an inverting compensation current. This compensation current is used to compensate the current of these current sources whose associated differential or holding stage (3, 4, 5, 6) is turned off. The proposed principle allows for a reduced supply voltage and, at the same time, a frequency divider for the gigahertz range thanks to the low parasitic capacitances of the circuit, which can be fully integrated using MOS circuit technology.

In particular, the flip-flop circuit known from this invention has two pairs of differential circuits in which MOS transistors of the same type are connected to the sources and whose drains are connected to the supply voltage through resistors. The gates of the transistors are connected to the drains of complementary transistors in a pair, and whose gates are connected to the drains of subsequent transistors in another pair. The flip-flop also has a third and fourth pair of transistors in which MOS transistors of the same type are connected to the sources and whose drains are connected sequentially to the drains of the transistors of the first two pairs. The gates of the transistors of the third pair are connected sequentially to the drains of the transistors of the fourth pair, and the gates of the transistors of the fourth pair are connected in reverse order to the drains of the transistors of the third pair.

The Miller divider is known in the art, for example from Meister, T, Ishida, K., Sou, A., Carta, C, & Ellinger, F. "3.93-MHz/328-nW dynamic frequency divider in flexible a-IGZO TFT technology", IEEE Solid-State Circuits Letters, 3, pp. 134-137, 2020, DOI: 10.1109/LSSC.2020.3008027, which presents an implementation of a dynamic frequency divider in fully flexible amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) technology on a sub-15 μm polyimide substrate. This frequency divider is regenerative and is also known as a Miller divider. It has differential inputs and differential outputs, and at least one differential circuit in which a-IGZO TFT "n"-type transistors are connected at the sources and whose drains are connected to the supply voltage via resistors. The paper demonstrates that the presented circuit is more energy-efficient than previous work in similar technologies and that it can be used as a fourth and later frequency divider stage in a 13.56 MHz RFID or NFC tag.

A master-slave flip-flop is known from the Japanese invention JPH0730381A. The aim of the invention was to create a master-slave flip-flop that could increase the maximum frequency without increasing the circuit area or increasing power consumption. The master-slave flip-flop comprises a master-side latch circuit 100 equipped with multiple FET transistors, a slave-side latch circuit 200, and a buffer circuit 300. The gate widths of the FET transistors forming the master-side latch circuit 100, the slave-side latch circuit 200, and the buffer circuit 300 are determined so that the output load capacity of the master-side latch circuit 100 becomes equal to the load capacity of the slave-side latch circuit 200.

Known in the art, particularly in electronics engineering, are (remote) RFID (radio-frequency identification) systems, and in particular NFC (near-field communication). Known in the art are insulated-gate field-effect transistors (FETs), thin-film transistors (TFTs), as well as transistors based on indium gallium zinc oxide (IGZO or InGaZnO - from indium (In), gallium (Ga), zinc (Zn), oxygen (O)). It is also known that the drain and source designations of these transistors are conventional, because due to the transistor's symmetrical structure, swapping these designations does not change the functionality of the transistor or the circuit in which it is located – however, this nomenclature is for clarity purposes.

The aim of the invention is to create a fast flip-flop for a divider that will solve the problem of too slow operation of a-IGZO TFT technology for RFID and NFC purposes, with relatively low power demand, small system area and low sensitivity to supply voltage disturbances.

The essence of the solution is that in a bistable flip-flop having a first pair of transistors and a second pair of transistors, where the drains of the transistors are connected to the supply terminal through resistors, in which pairs the transistors are connected to each other by sources, and each transistor gate is connected to the drain of the second transistor in a given pair, and having a third pair of transistors and a fourth pair of transistors, where the transistors in the pairs are connected to each other by sources, and the combined sources are connected to the drains of the clock transistors so that the sources of the third pair of transistors are connected to the clock transistor whose gate is connected to the non-negated input terminal, and the sources of the fourth pair of transistors are connected to the clock transistor whose gate is connected to the negated input terminal, wherein the drains of the transistors of the third pair are connected in turn to the drains of the transistors of the first pair, and the drains The transistors of the fourth pair are connected in sequence to the drains of the transistors of the second pair, while the gates of the transistors of the third pair are connected in sequence to the drains of the transistors of the fourth pair, and the gates of the transistors of the fourth pair are connected in reverse order to the drains of the transistors of the third pair, wherein the non-negated output terminal is connected to the drain of the second transistor of the fourth pair, and the negated output terminal is connected to the drain of the first transistor of the fourth pair, according to the invention, the sources of the transistors of the first and second pair are connected to the circuit ground, and the sources of the clock transistors are connected to the circuit ground, and the charge injection terminal is connected to the drain of the second clock transistor.

The technical effect of such a system is that the flip-flop is two-stage, differential, D-type and does not require additional subsystems, so it has a very small number of components and is also fast and energy-efficient.

However, the ability to inject charge allows for additional system speed.

Preferably, the flip-flop is equipped with a set input terminal connected to the gates of two transistors, whose sources are connected to the circuit ground. The drain of the first transistor is connected to the drain of the first transistor of the fourth pair, while the drain of the second transistor is connected to the drain of the first transistor of the third pair. This allows for pre-setting of the flip-flop's logical value.

Advantageously, the flip-flop operates primarily at a 13.56 MHz input signal frequency. This allows the system to be used to implement the NFC standard.

Preferably, the system's power supply voltage is the voltage derived from the radio signal harvesting. The voltage derived from the radio signal harvesting is usually far from the ideal supply voltage because it is distorted by the carrier frequency signal, and its fundamental amplitude can vary depending on the antenna's distance from the source, the received modulation, and the modulation being performed. Therefore, the system must be immune to such interference and disturbances.

Preferably, all transistors in the circuit are "n" type FETs. The use of a single type of FET with an insulated gate simplifies the technological process of implementing the circuit.

Preferably, all transistors in the circuit are TFTs. The use of TFTs allows for the construction of a low-cost and/or flexible integrated circuit.

Preferably, the transistor channels are made of an amorphous semiconductor material. The use of amorphous semiconductor material ensures low-cost transistor fabrication (at relatively low temperatures).

Preferably, the transistors contain indium gallium zinc oxide. The use of indium gallium zinc oxide (IGZO) provides a relatively high carrier mobility parameter.

Preferably, the transistors of the first and second pairs are identical in their channel width-to-length ratio. The transistors of the third pair are identical in their channel width-to-length ratio, with this ratio being 2 to 4 times greater than the first two pairs. The transistors of the fourth pair are identical in their channel width-to-length ratio, with this ratio being 1.5 to 2.5 times greater than the first two pairs. The clock transistors have a channel width-to-length ratio 3 to 5 times greater than the first two pairs. These transistor dimensional ratios minimize the settling and hold times when writing data to the master and slave sections. Furthermore, the quiescent power of the flip-flop is low.

An example of the implementation is shown in the drawing, where Fig. 1 shows a schematic diagram of a bistable flip-flop.

The bistable flip-flop in the embodiment shown in Fig. 1 has the first two pairs of transistors, T2 and T3, and T7 and T8, connected by their drains to the HRV supply terminal through resistors R1, R2, R3, and R4. The transistors in the pairs are connected to each other by their sources, T2 and T3, and T7 and T8, which are connected to ground (GND). Each transistor gate is connected to the drain of the second transistor in a given pair. The flip-flop also has two further pairs of transistors, T1 and T4, and T6 and T9, where the transistors in the pairs are connected by their sources, and the sources are connected to the drains of clock transistors T5 and T10, whose sources are connected to ground (GND). The gate of the first clock transistor, T5, is connected to the non-inverted CLK input terminal of the flip-flop, and the gate of the second, T10, is connected to the non-inverted nCLK input terminal. The drains of transistors in the third pair, T1 and T4, are connected sequentially to the drains of transistors in the first pair, T2 and T3. The drains of transistors in the fourth pair, T6 and T9, are connected sequentially to the drains of transistors in the second pair, T7 and T8. The gates of transistors in the third pair, T1 and T4, are connected sequentially to the drains of transistors in the fourth pair, T6 and T9, and the gates of transistors in the fourth pair, T6 and T9, are connected in reverse order to the drains of transistors in the third pair, T1 and T4. The non-inverted Q output terminal of the flip-flop is connected to the drain of the second transistor in the fourth pair, T9, and the non-inverted nQ output terminal is connected to the drain of the first transistor in the fourth pair, T6. The charge injection terminal Cl is connected to the drain of the second clock transistor T10. The flip-flop is also equipped with a setting input terminal Set, which is connected to the gates of two transistors Ts1 and Ts2, whose sources are connected to the ground of the circuit, and the drain of the first transistor Ts1 is connected to the drain of the first transistor of the fourth pair T6, while the drain of the second transistor Ts2 is connected to the drain of the first transistor of the third pair T1.

Although the overall design of the flip-flop is similar for each dedicated divider stage, each divider stage is implemented to its specific needs, using different transistor sizes—for example, different sizes of transistors T2, T3, T7, and T8 to hold (within the positive feedback loop) and toggle logical states (transistors T1, T4, T6, and T9) during active clock edges. Using the minimum allowable transistor sizes (W = 5 μm, L = 0.8 μm) in the flip-flop feedback loops and larger transistor sizes (W > 8 μm, L = 0.8 μm) for dynamic data switching minimizes the static power consumption of the entire divider.

Furthermore, depending on whether the flip-flop is used as the first or second stage, the main differences lie in the additional charge injection mechanism (Cl) and the integrated circuit topography, which minimizes parasitic capacitances. The first, fastest stage utilizes the upper metallization layers to minimize parasitic capacitances at the intersections of the lower metallization traces. When the flip-flop is used as the first stage, the gate of transistor T5 (the non-inverted CLK input) is driven directly by the RF antenna, which provides higher instantaneous currents responsible for the flow of charge in its gate-source capacitances. This is in contrast to the gate-source capacitance of transistor T10 (the inverted nCLK input), which must be driven indirectly by the inverting circuit. To accelerate the switching of this transistor T10, the Cl input injects an additional charge into the gate-source capacitances of transistors T6 and T9 during the falling edge of the RF signal.

A logical one on the CLK clock lowers the source potentials of transistors T1 and T4, moving T1 into the triode region, causing a rapid voltage drop across T1, causing T3 to cut off and initiating the overshoot process in the T2-T3 pair. The beginning of the T2-T3 switching process is visible when the drain voltage of transistor T3 begins to rise, and the positive feedback loop tends to overdrive the gate of T2, accelerating the cutoff of T3. This process continues continuously as long as a logical one is present at the non-inverted input of the CLK clock. Conversely, a logical one on the inverted input of the nCLK clock lowers the source potentials of T6 and T9, and ultimately turns on T6 due to the previous switching at the drain of T3. The entire switching process repeats every half-cycle of the carrier wave.

Due to the relatively large gate-source capacitances of transistors T6 and T9, which constitute the load on the drain of transistor T10, and the presence of its gate-drain capacitance, a compensation mechanism using the Cl input was proposed. Whenever the clock signal imposes a rising edge on the gate of T10 and the drain of T10 lowers the capacitances of T6 and T9, a falling edge occurs on the RF signal. Therefore, it is recommended to use an additional capacitance between the RF signal and the Cl input to compensate for the capacitive load on the drain of T10, thereby accelerating the T10 switching process.

It should also be noted that the slave block of the flip-flop, i.e., T7-T8, is designed to operate at the carrier frequency with minimal power dissipation. Therefore, the outputs of the entire master-slave flip-flop, i.e., Q and nQ, (i.e., the drains of T8 and T7) of the first divider stage, are not designed to efficiently drive large capacitive loads at a slew rate corresponding to half the carrier frequency. Therefore, using these outputs at the circuit's limiting frequencies may require additional signal amplification.

Using the Set input allows for presetting the flip-flop's logical value, which, with multiple stages of this type in a frequency divider, allows for phase adjustment of the divider's clock signal. It is also possible to optimize power consumption depending on the frequency at which a given stage (flip-flop) must operate. This is achieved by selecting the W/L ratio of the transistors and their corresponding drain resistors.

The invention allows for the carrier frequency of an RFID radio signal to be divided and utilized in the frequency divider using a single type of low-speed transistors, specifically a technological process using a-IGZO TFTs. Industrial applications of the invention are found in the industry and market for products requiring individual electronic labeling.

Claims (9)

1. A bistable flip-flop having a first pair of transistors (T2, T3) and a second pair of transistors (T7, T8), wherein the drains of the transistors (T2, T3, T7, T8) are connected to a supply terminal (HRV) through resistors (R1, R2, R3, R4), in which pairs the transistors are connected to each other by sources (T2, T3), (T7, T8), and each transistor gate is connected to the drain of the second transistor in a given pair, and having a third pair of transistors (T1, T4) and a fourth pair of transistors (T6, T9), wherein the transistors in the pairs are connected to each other by sources (T1, T4), (T6, T9), and the combined sources are connected to the drains of the clock transistors so that the sources of the third pair of transistors (T1, T4) are connected to the clock transistor (T5), whose gate is connected to the non-inverted input terminal (CLK), and the sources of the fourth pair of transistors (T6, T9) are connected to the clock transistor (T10), whose gate is connected to the non-inverted input terminal (nCLK), wherein the drains of the transistors of the third pair (T1, T4) are connected sequentially to the drains of the transistors of the first pair (T2, T3), and the drains of the transistors of the fourth pair (T6, T9) are connected sequentially to the drains of the transistors of the second pair (T7, T8), while the gates of the transistors of the third pair (T1, T4) are connected sequentially to the drains of the transistors of the fourth pair (T6, T9), and the gates of the transistors of the fourth pair (T6, T9) are connected in reverse order to the drains of the transistors of the third pair (T1, T4), wherein the non-inverted output terminal (Q) is connected to the drain of the second the transistor of the fourth pair (T9), and the negated output terminal (nQ) is connected to the drain of the first transistor of the fourth pair (T6), characterized in that the sources of the transistors of the first and second pair (T2, T3, T7, T8) are connected to the ground of the system (gnd), and in that the sources of the clock transistors (T5, T10) are connected to the ground of the system (gnd), and in that the charge injection terminal (Cl) is connected to the drain of the second clock transistor (T10). 2. A bistable flip-flop according to claim 1, characterized in that it is equipped with a setting input terminal (Set), which is connected to the gates of two transistors (Ts1, Ts2), the sources of which are connected to the ground of the system, and the drain of the first transistor (Ts1) is connected to the drain of the first transistor of the fourth pair (T6), while the drain of the second transistor (Ts2) is connected to the drain of the first transistor of the third pair (T1). 3. A bistable flip-flop according to claim 1 or 2, characterized in that it operates substantially at a frequency of 13.56 MHz of the input signal. 4. A bistable flip-flop according to claim 1, 2 or 3, characterized in that the supply voltage of the system is a voltage derived from the harvesting of a radio signal. 5. A bistable flip-flop according to any one of claims 1 to 4, characterized in that all transistors in the circuit are "n" type FET transistors. 6. A bistable flip-flop according to any of claims 1 to 5, characterized in that all transistors in the circuit are TFT transistors. 7. A bistable flip-flop according to any one of claims 1 to 6, characterized in that the transistor channels are made of an amorphous semiconductor material. 8. A bistable flip-flop according to any one of claims 1 to 7, characterized in that the transistors comprise indium gallium zinc oxide. 9. A bistable flip-flop according to any one of claims 1 to 8, characterized in that the transistors of the first and second pairs (T2, T3), (T7, T8) are the same with respect to the ratio of the channel width to the length, and in that the transistors of the third pair (T1, T4) are the same with respect to the ratio of the channel width to the length, this ratio being 2 to 4 times greater than the first two pairs, and in that the transistors of the fourth pair (T6, T9) are the same with respect to the ratio of the channel width to the length, this ratio being 1.5 to 2.5 times greater than the first two pairs, and in that the clock transistors (T5, T10) have a ratio of the channel width to the length 3 to 5 times greater than the first two pairs.