PL450733A3 - Metastability random generator - Google Patents

Metastability random generator

Info

Publication number
PL450733A3
PL450733A3 PL450733A PL45073324A PL450733A3 PL 450733 A3 PL450733 A3 PL 450733A3 PL 450733 A PL450733 A PL 450733A PL 45073324 A PL45073324 A PL 45073324A PL 450733 A3 PL450733 A3 PL 450733A3
Authority
PL
Poland
Prior art keywords
flip
flop
regulation
arbiter
metastability
Prior art date
Application number
PL450733A
Other languages
Polish (pl)
Inventor
Piotr Z. Wieczorek
Krzysztof Gołofit
Original Assignee
Politechnika Warszawska
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from PL422480A external-priority patent/PL232382B1/en
Priority claimed from PL422477A external-priority patent/PL232380B1/en
Priority claimed from PL422479A external-priority patent/PL232381B1/en
Priority claimed from PL422478A external-priority patent/PL232335B1/en
Application filed by Politechnika Warszawska filed Critical Politechnika Warszawska
Publication of PL450733A3 publication Critical patent/PL450733A3/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/84—Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Bus Control (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Control Of Eletrric Generators (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

Zgłoszenie dotyczy arbitra (ARB) metastabilnościowego generatora losowego i sposobów regulacji pracą arbitra, zbudowanego z dwóch przerzutników (P1, P2) komplementarnie podłączonych do jego wejść (i1-A, i2-A) oraz elementów logicznych (AND, NOT, XNOR) dołączonych do wyjść przerzutników (Q1, Q2) i zamieniających pierwszeństwo na logiczne wartości oraz wykrywających wewnętrzny błąd arbitrażu. Wskutek błędu odcinane jest wyjście arbitra (o-A) przez bufor trójstanowy (B), a błędy arbitrażu zapisywane są w rejestrze przesuwnym. Pracą przerzutników steruje układ kompensacji i regulacji (UKR), który dzięki specjalnej budowie przerzutników pozwala na: regulację szybkości jednego przerzutnika względem drugiego, regulację pracy między stopniem master i slave w każdym przerzutniku, równoważenie pracy każdego stopnia każdego przerzutnika, wzorcowanie arbitra, kompensację w trakcie pracy, czy regulację pobieranej mocy. Dzięki zgłoszeniu możliwa jest kompensacja rozrzutów technologicznych, zmiana położenia i rozmiaru okna metastabilności, regulacja wpływu szumu fazowego, redukcja czasu regeneracji, kompensacja wpływu starzenia się i pracy mechanicznej czy oddziaływania czynników środowiskowych.This application concerns an arbitrator (ARB) for a metastability random generator and methods for regulating the operation of an arbitrator. The arbiter consists of two flip-flops (P1, P2) complementarily connected to its inputs (i1-A, i2-A) and logical elements (AND, NOT, XNOR) connected to the flip-flop outputs (Q1, Q2), converting priority to logical values and detecting an internal arbitration error. As a result of an error, the arbiter output (o-A) is cut off by a three-state buffer (B), and arbitration errors are stored in a shift register. The operation of the flip-flops is controlled by a compensation and regulation circuit (UKR), which, thanks to its special design, allows for: speed regulation of one flip-flop relative to the other, regulation of the master and slave stages in each flip-flop, balancing the operation of each stage of each flip-flop, calibration of the arbiter, compensation during operation, and power consumption regulation. Thanks to the notification, it is possible to compensate for technological dispersion, change the position and size of the metastability window, regulate the influence of phase noise, reduce the regeneration time, compensate for the influence of aging and mechanical work or the impact of environmental factors.

PL450733A 2017-08-08 2024-12-27 Metastability random generator PL450733A3 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
PL422480A PL232382B1 (en) 2017-08-08 2017-08-08 Metastability random generator
PL422477A PL232380B1 (en) 2017-08-08 2017-08-08 Generator of metastability time intervals
PL422479A PL232381B1 (en) 2017-08-08 2017-08-08 Metastability random generator
PL422478A PL232335B1 (en) 2017-08-08 2017-08-08 Arbiter
PCT/IB2018/055941 WO2019030668A1 (en) 2017-08-08 2018-08-07 Metastability based random number generator

Publications (1)

Publication Number Publication Date
PL450733A3 true PL450733A3 (en) 2026-01-19

Family

ID=65271936

Family Applications (3)

Application Number Title Priority Date Filing Date
PL428402A PL241527B1 (en) 2017-08-08 2018-08-07 Metastability random generator
PL450733A PL450733A3 (en) 2017-08-08 2024-12-27 Metastability random generator
PL450732A PL450732A3 (en) 2017-08-08 2024-12-27 Metastability random generator

Family Applications Before (1)

Application Number Title Priority Date Filing Date
PL428402A PL241527B1 (en) 2017-08-08 2018-08-07 Metastability random generator

Family Applications After (1)

Application Number Title Priority Date Filing Date
PL450732A PL450732A3 (en) 2017-08-08 2024-12-27 Metastability random generator

Country Status (2)

Country Link
PL (3) PL241527B1 (en)
WO (1) WO2019030668A1 (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07169269A (en) * 1993-12-14 1995-07-04 Matsushita Electric Ind Co Ltd Arbiter control circuit
KR100762264B1 (en) * 2005-06-14 2007-10-01 충남대학교산학협력단 Bus Matrix Structure Reduces Latency
PL225186B1 (en) * 2012-11-08 2017-02-28 Politechnika Warszawska Meta-stability intervals generator
PL224925B1 (en) * 2012-11-08 2017-02-28 Politechnika Warszawska Arbitrator

Also Published As

Publication number Publication date
PL241527B1 (en) 2022-10-17
WO2019030668A1 (en) 2019-02-14
PL450732A3 (en) 2026-01-19
PL428402A1 (en) 2020-02-24

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