SE9300624L - Signalbehandlingskrets och förfarande för fördröjning av en binär periodisk insignal - Google Patents

Signalbehandlingskrets och förfarande för fördröjning av en binär periodisk insignal

Info

Publication number
SE9300624L
SE9300624L SE9300624A SE9300624A SE9300624L SE 9300624 L SE9300624 L SE 9300624L SE 9300624 A SE9300624 A SE 9300624A SE 9300624 A SE9300624 A SE 9300624A SE 9300624 L SE9300624 L SE 9300624L
Authority
SE
Sweden
Prior art keywords
delay
input signal
delay devices
devices
processing circuit
Prior art date
Application number
SE9300624A
Other languages
Unknown language ( )
English (en)
Other versions
SE9300624D0 (sv
SE500929C2 (sv
Inventor
Nils Per Aake Liedberg
Original Assignee
Ellemtel Utvecklings Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ellemtel Utvecklings Ab filed Critical Ellemtel Utvecklings Ab
Priority to SE9300624A priority Critical patent/SE500929C2/sv
Publication of SE9300624D0 publication Critical patent/SE9300624D0/sv
Priority to CN94191276A priority patent/CN1118205A/zh
Priority to JP6518873A priority patent/JPH08506949A/ja
Priority to EP94908535A priority patent/EP0686319A1/en
Priority to CA002154252A priority patent/CA2154252A1/en
Priority to BR9406373A priority patent/BR9406373A/pt
Priority to PCT/SE1994/000088 priority patent/WO1994019868A1/en
Priority to AU61587/94A priority patent/AU676022B2/en
Priority to MXPA94001092A priority patent/MXPA94001092A/es
Priority to US08/201,851 priority patent/US5471165A/en
Priority to KR1019950703580A priority patent/KR960701512A/ko
Publication of SE9300624L publication Critical patent/SE9300624L/sv
Publication of SE500929C2 publication Critical patent/SE500929C2/sv
Priority to FI953953A priority patent/FI953953A7/sv
Priority to NO953307A priority patent/NO953307L/no

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/06—Frequency or rate modulation, i.e. PFM or PRM

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Manipulation Of Pulses (AREA)
SE9300624A 1993-02-24 1993-02-24 Signalbehandlingskrets och förfarande för fördröjning av en binär periodisk insignal SE500929C2 (sv)

Priority Applications (13)

Application Number Priority Date Filing Date Title
SE9300624A SE500929C2 (sv) 1993-02-24 1993-02-24 Signalbehandlingskrets och förfarande för fördröjning av en binär periodisk insignal
JP6518873A JPH08506949A (ja) 1993-02-24 1994-02-04 ２進の周期的入力信号を遅延させる信号処理回路と方法
PCT/SE1994/000088 WO1994019868A1 (en) 1993-02-24 1994-02-04 A signal processing circuit and a method of delaying a binary periodic input signal
AU61587/94A AU676022B2 (en) 1993-02-24 1994-02-04 A signal processing circuit and a method of delaying a binary periodic input signal
EP94908535A EP0686319A1 (en) 1993-02-24 1994-02-04 A signal processing circuit and a method of delaying a binary periodic input signal
CA002154252A CA2154252A1 (en) 1993-02-24 1994-02-04 A signal processing circuit and a method of delaying a binary periodic input signal
BR9406373A BR9406373A (pt) 1993-02-24 1994-02-04 Processo de retardar um sinal de entrada periódico binário e circuito de processamento de sinal digital
CN94191276A CN1118205A (zh) 1993-02-24 1994-02-04 信号处理电路和延时二进制周期输入信号的方法
MXPA94001092A MXPA94001092A (es) 1993-02-24 1994-02-11 Un circuito de procesamiento de senales y un metodo para retardar una senal de entrada periodica binaria.
US08/201,851 US5471165A (en) 1993-02-24 1994-02-24 Signal processing circuit and a method of delaying a binary periodic input signal
KR1019950703580A KR960701512A (ko) 1993-02-24 1994-02-24 신호처리회로 및 2진 주기입력신호 지연방법(a signal processing circuit and a method of delaying a binary periodic input signal)
FI953953A FI953953A7 (sv) 1993-02-24 1995-08-23 Signalprocessorkrets samt ett förfarande för att fördröja en binär, periodisk ingångssignal
NO953307A NO953307L (no) 1993-02-24 1995-08-23 Signalprosseseringskrets og fremgangsmåte ved forsinkelse av et binært innsignal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9300624A SE500929C2 (sv) 1993-02-24 1993-02-24 Signalbehandlingskrets och förfarande för fördröjning av en binär periodisk insignal

Publications (3)

Publication Number Publication Date
SE9300624D0 SE9300624D0 (sv) 1993-02-24
SE9300624L true SE9300624L (sv) 1994-08-25
SE500929C2 SE500929C2 (sv) 1994-10-03

Family

ID=20389021

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9300624A SE500929C2 (sv) 1993-02-24 1993-02-24 Signalbehandlingskrets och förfarande för fördröjning av en binär periodisk insignal

Country Status (13)

Country Link
US (1) US5471165A (sv)
EP (1) EP0686319A1 (sv)
JP (1) JPH08506949A (sv)
KR (1) KR960701512A (sv)
CN (1) CN1118205A (sv)
AU (1) AU676022B2 (sv)
BR (1) BR9406373A (sv)
CA (1) CA2154252A1 (sv)
FI (1) FI953953A7 (sv)
MX (1) MXPA94001092A (sv)
NO (1) NO953307L (sv)
SE (1) SE500929C2 (sv)
WO (1) WO1994019868A1 (sv)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2710800B1 (fr) * 1993-09-27 1995-12-15 Sgs Thomson Microelectronics Ligne à retard numérique.
JP3639000B2 (ja) * 1995-06-13 2005-04-13 富士通株式会社 位相合わせ装置及び遅延制御回路
JPH10117142A (ja) * 1996-10-11 1998-05-06 Fujitsu Ltd 位相同期ループ回路および半導体集積回路
JPH1131964A (ja) * 1997-07-11 1999-02-02 Hitachi Ltd 論理回路
US6128680A (en) * 1997-12-18 2000-10-03 Alcatel Usa Sourcing, L.P. Apparatus and method of sharing a state machine for input and output signal processing
US6144034A (en) * 1998-07-22 2000-11-07 Adac Laboratories Delay calibration for gamma camera timing circuit
EP1001533B1 (en) * 1998-11-14 2001-09-26 Agilent Technologies Inc. a Delaware Corporation Timing generator
DE19933115A1 (de) * 1999-07-19 2001-01-25 Mannesmann Vdo Ag Verfahren zur Modulation eines Grundtaktes für digitale Schaltungen und Taktmodulator zur Ausführung des Verfahrens
US7805628B2 (en) * 2001-04-02 2010-09-28 Credence Systems Corporation High resolution clock signal generator
US20040232954A1 (en) * 2001-07-06 2004-11-25 Van Zeijl Paulus Thomas Signal generator device, method for generating a signal and devices including such a signal generator device
US7020792B2 (en) * 2002-04-30 2006-03-28 Intel Corporation Method and apparatus for time domain equalization
WO2003098414A1 (en) * 2002-05-16 2003-11-27 Infineon Technologies Ag Apparatus for adjusting the phase of a digital signal
KR100493046B1 (ko) * 2003-02-04 2005-06-07 삼성전자주식회사 클럭의 듀티 사이클을 조정할 수 있는 주파수 체배기 및체배방법
US7109768B2 (en) * 2004-06-29 2006-09-19 Intel Corporation Closed-loop control of driver slew rate
US8842766B2 (en) * 2010-03-31 2014-09-23 Texas Instruments Incorporated Apparatus and method for reducing interference signals in an integrated circuit using multiphase clocks
CN101895274B (zh) * 2010-07-21 2013-04-10 珠海天威技术开发有限公司 数字滤波电路及其滤波方法、耗材芯片
CN104079274A (zh) * 2013-03-26 2014-10-01 佛山市顺德区顺达电脑厂有限公司 分析用信号延时装置及其方法
CN108390666A (zh) * 2018-04-26 2018-08-10 佛山科学技术学院 一种延时电路
US10998892B1 (en) * 2020-08-13 2021-05-04 Realtek Semiconductor Corp. Frequency doubler with duty cycle control and method thereof
CN114826258A (zh) * 2021-01-29 2022-07-29 浙江杭可仪器有限公司 一种高频波形信号生成方法及其生成系统

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3993957A (en) * 1976-03-08 1976-11-23 International Business Machines Corporation Clock converter circuit
US4494021A (en) * 1982-08-30 1985-01-15 Xerox Corporation Self-calibrated clock and timing signal generator for MOS/VLSI circuitry
JPS5972814A (ja) * 1982-10-20 1984-04-24 Sanyo Electric Co Ltd 遅延回路
JPS61163715A (ja) * 1985-01-14 1986-07-24 Nec Corp 遅延線を用いた多相クロツク発生回路
JPS6270922A (ja) * 1985-09-04 1987-04-01 Fujitsu Ltd クロツク位相調整方式
US4795985A (en) * 1986-04-01 1989-01-03 Hewlett-Packard Company Digital phase lock loop
CA1254957A (en) * 1986-11-07 1989-05-30 Mitel Corporation Frequency doubler
US5173617A (en) * 1988-06-27 1992-12-22 Motorola, Inc. Digital phase lock clock generator without local oscillator
EP0476585B1 (en) * 1990-09-18 1998-08-26 Fujitsu Limited Electronic device using a reference delay generator
US5159205A (en) * 1990-10-24 1992-10-27 Burr-Brown Corporation Timing generator circuit including adjustable tapped delay line within phase lock loop to control timing of signals in the tapped delay line
JPH07142997A (ja) * 1990-11-29 1995-06-02 Internatl Business Mach Corp <Ibm> ディレイ・ライン較正回路
US5223755A (en) * 1990-12-26 1993-06-29 Xerox Corporation Extended frequency range variable delay locked loop for clock synchronization
US5095233A (en) * 1991-02-14 1992-03-10 Motorola, Inc. Digital delay line with inverter tap resolution
US5295164A (en) * 1991-12-23 1994-03-15 Apple Computer, Inc. Apparatus for providing a system clock locked to an external clock over a wide range of frequencies
US5250913A (en) * 1992-02-21 1993-10-05 Advanced Micro Devices, Inc. Variable pulse width phase detector
US5365130A (en) * 1992-08-07 1994-11-15 Vlsi Technology, Inc. Self-compensating output pad for an integrated circuit and method therefor

Also Published As

Publication number Publication date
MXPA94001092A (es) 2004-08-20
KR960701512A (ko) 1996-02-24
JPH08506949A (ja) 1996-07-23
SE9300624D0 (sv) 1993-02-24
CN1118205A (zh) 1996-03-06
EP0686319A1 (en) 1995-12-13
BR9406373A (pt) 1996-01-16
WO1994019868A1 (en) 1994-09-01
US5471165A (en) 1995-11-28
AU676022B2 (en) 1997-02-27
CA2154252A1 (en) 1994-09-01
FI953953A0 (sv) 1995-08-23
AU6158794A (en) 1994-09-14
NO953307D0 (no) 1995-08-23
SE500929C2 (sv) 1994-10-03
NO953307L (no) 1995-10-19
FI953953A7 (sv) 1995-08-23

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