SG111156A1 - Method of forming a high performance and low cost cmos device - Google Patents

Method of forming a high performance and low cost cmos device

Info

Publication number
SG111156A1
SG111156A1 SG200305764A SG200305764A SG111156A1 SG 111156 A1 SG111156 A1 SG 111156A1 SG 200305764 A SG200305764 A SG 200305764A SG 200305764 A SG200305764 A SG 200305764A SG 111156 A1 SG111156 A1 SG 111156A1
Authority
SG
Singapore
Prior art keywords
forming
low cost
high performance
cmos device
cost cmos
Prior art date
Application number
SG200305764A
Other languages
English (en)
Inventor
Zhen Zheng Jia
Yun Siah Soh
Choo Hsia Liang
Hua Lim Eng
Chooi Simon
Hoe Ang Chew
Original Assignee
Chartered Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chartered Semiconductor Mfg filed Critical Chartered Semiconductor Mfg
Publication of SG111156A1 publication Critical patent/SG111156A1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H10D30/0229—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET forming drain regions and lightly-doped drain [LDD] simultaneously, e.g. using implantation through a T-shaped mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0174—Manufacturing their gate conductors the gate conductors being silicided
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0184—Manufacturing their gate sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
SG200305764A 2002-10-01 2003-09-25 Method of forming a high performance and low cost cmos device SG111156A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/262,169 US6762085B2 (en) 2002-10-01 2002-10-01 Method of forming a high performance and low cost CMOS device

Publications (1)

Publication Number Publication Date
SG111156A1 true SG111156A1 (en) 2005-05-30

Family

ID=31993547

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200305764A SG111156A1 (en) 2002-10-01 2003-09-25 Method of forming a high performance and low cost cmos device

Country Status (4)

Country Link
US (1) US6762085B2 (fr)
EP (1) EP1406295A3 (fr)
JP (1) JP2004274022A (fr)
SG (1) SG111156A1 (fr)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2846789B1 (fr) * 2002-11-05 2005-06-24 St Microelectronics Sa Dispositif semi-conducteur a transistors mos a couche d'arret de gravure ayant un stress residuel ameliore et procede de fabrication d'un tel dispositif semi-conducteur
US7045408B2 (en) * 2003-05-21 2006-05-16 Intel Corporation Integrated circuit with improved channel stress properties and a method for making it
US6905923B1 (en) * 2003-07-15 2005-06-14 Advanced Micro Devices, Inc. Offset spacer process for forming N-type transistors
US6987061B2 (en) * 2003-08-19 2006-01-17 Texas Instruments Incorporated Dual salicide process for optimum performance
US7018928B2 (en) * 2003-09-04 2006-03-28 Taiwan Semiconductor Manufacturing Co., Ltd. Plasma treatment method to reduce silicon erosion over HDI silicon regions
US7135373B2 (en) * 2003-09-23 2006-11-14 Texas Instruments Incorporated Reduction of channel hot carrier effects in transistor devices
TWI231989B (en) * 2003-11-18 2005-05-01 Promos Technologies Inc Method of fabricating a MOSFET device
US7235848B2 (en) * 2003-12-09 2007-06-26 Applied Intellectual Properties Co., Ltd. Nonvolatile memory with spacer trapping structure
US7049200B2 (en) * 2004-05-25 2006-05-23 Applied Materials Inc. Method for forming a low thermal budget spacer
US7230296B2 (en) * 2004-11-08 2007-06-12 International Business Machines Corporation Self-aligned low-k gate cap
JP4482428B2 (ja) * 2004-11-12 2010-06-16 川崎マイクロエレクトロニクス株式会社 半導体集積回路の製造方法および半導体集積回路
US7227234B2 (en) * 2004-12-14 2007-06-05 Tower Semiconductor Ltd. Embedded non-volatile memory cell with charge-trapping sidewall spacers
US20060160317A1 (en) * 2005-01-18 2006-07-20 International Business Machines Corporation Structure and method to enhance stress in a channel of cmos devices using a thin gate
US7858458B2 (en) 2005-06-14 2010-12-28 Micron Technology, Inc. CMOS fabrication
JP4772456B2 (ja) * 2005-11-04 2011-09-14 東京エレクトロン株式会社 半導体装置の製造方法、半導体装置の製造装置、制御プログラム及びコンピュータ記憶媒体
US7759206B2 (en) * 2005-11-29 2010-07-20 International Business Machines Corporation Methods of forming semiconductor devices using embedded L-shape spacers
US20070224745A1 (en) * 2006-03-21 2007-09-27 Hui-Chen Chang Semiconductor device and fabricating method thereof
US7678636B2 (en) * 2006-06-29 2010-03-16 Taiwan Semiconductor Manufacturing Company, Ltd. Selective formation of stress memorization layer
JP2008091536A (ja) 2006-09-29 2008-04-17 Toshiba Corp 半導体装置及びその製造方法
CN100594600C (zh) * 2007-02-15 2010-03-17 联华电子股份有限公司 互补式金属氧化物半导体晶体管及其制作方法
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
JP5096055B2 (ja) * 2007-07-02 2012-12-12 ローム株式会社 Ｃｍｏｓ型半導体集積回路の製造方法
US8101479B2 (en) * 2009-03-27 2012-01-24 National Semiconductor Corporation Fabrication of asymmetric field-effect transistors using L-shaped spacers
US8324110B2 (en) * 2010-02-02 2012-12-04 International Business Machines Corporation Field effect transistor (FET) and method of forming the FET without damaging the wafer surface
US8444255B2 (en) 2011-05-18 2013-05-21 Hewlett-Packard Development Company, L.P. Power distribution in a thermal ink jet printhead
CN103187254B (zh) * 2011-12-28 2015-12-02 北大方正集团有限公司 一种双多晶硅栅的制造方法
US9508716B2 (en) * 2013-03-14 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of manufacturing a semiconductor device
KR102050214B1 (ko) * 2013-06-13 2019-12-02 삼성전자 주식회사 반도체 소자 제조 방법
CN108630740B (zh) * 2017-03-16 2021-07-09 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US10304683B2 (en) * 2017-10-31 2019-05-28 Globalfoundries Inc. Early gate silicidation in transistor elements
US20220093740A1 (en) * 2020-09-18 2022-03-24 Qualcomm Incorporated High-power field-effect transistor (fet)
CN112908855B (zh) * 2021-01-28 2024-06-11 上海华力集成电路制造有限公司 一种提升p管组件负偏压温度不稳定性的方法
US12034054B2 (en) * 2021-03-25 2024-07-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method for forming the same
US11646353B1 (en) * 2021-12-27 2023-05-09 Nanya Technology Corporation Semiconductor device structure
US12250833B2 (en) 2021-12-27 2025-03-11 Nanya Technology Corporation Method for manufacturing semiconductor device structure
CN116169027A (zh) * 2023-02-02 2023-05-26 武汉新芯集成电路制造有限公司 半导体装置的制作方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4728617A (en) * 1986-11-04 1988-03-01 Intel Corporation Method of fabricating a MOSFET with graded source and drain regions
GB2214349B (en) * 1988-01-19 1991-06-26 Standard Microsyst Smc Process for fabricating mos devices
DE69121535T2 (de) * 1990-12-07 1997-01-02 At & T Corp Feldeffekttransistor mit inverser T-förmiger Silizid-Torelektrode
JP3307972B2 (ja) * 1992-02-03 2002-07-29 シャープ株式会社 電界効果トランジスタの作製方法および電界効果トランジスタ
JPH06326122A (ja) * 1993-05-17 1994-11-25 Matsushita Electric Ind Co Ltd Ｍｏｓ型半導体装置およびその製造方法
US5668024A (en) * 1996-07-17 1997-09-16 Taiwan Semiconductor Manufacturing Company CMOS device structure with reduced risk of salicide bridging and reduced resistance via use of a ultra shallow, junction extension, ion implantation process
US6251764B1 (en) * 1999-11-15 2001-06-26 Chartered Semiconductor Manufacturing Ltd. Method to form an L-shaped silicon nitride sidewall spacer
US6319783B1 (en) * 1999-11-19 2001-11-20 Chartered Semiconductor Manufatcuring Ltd. Process to fabricate a novel source-drain extension
US6156598A (en) * 1999-12-13 2000-12-05 Chartered Semiconductor Manufacturing Ltd. Method for forming a lightly doped source and drain structure using an L-shaped spacer
US6346468B1 (en) * 2000-02-11 2002-02-12 Chartered Semiconductor Manufacturing Ltd. Method for forming an L-shaped spacer using a disposable polysilicon spacer
US6277683B1 (en) * 2000-02-28 2001-08-21 Chartered Semiconductor Manufacturing Ltd. Method of forming a sidewall spacer and a salicide blocking shape, using only one silicon nitride layer
US6348387B1 (en) * 2000-07-10 2002-02-19 Advanced Micro Devices, Inc. Field effect transistor with electrically induced drain and source extensions

Also Published As

Publication number Publication date
EP1406295A3 (fr) 2008-09-10
JP2004274022A (ja) 2004-09-30
US6762085B2 (en) 2004-07-13
US20040063264A1 (en) 2004-04-01
EP1406295A2 (fr) 2004-04-07

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