SG122908A1 - Method for fabricating a germanium on insulator (geoi) type wafer - Google Patents

Method for fabricating a germanium on insulator (geoi) type wafer

Info

Publication number
SG122908A1
SG122908A1 SG200507154A SG200507154A SG122908A1 SG 122908 A1 SG122908 A1 SG 122908A1 SG 200507154 A SG200507154 A SG 200507154A SG 200507154 A SG200507154 A SG 200507154A SG 122908 A1 SG122908 A1 SG 122908A1
Authority
SG
Singapore
Prior art keywords
germanium
substrate
handle
source
insulator
Prior art date
Application number
SG200507154A
Other languages
English (en)
Inventor
Konstantin Bourdelle
Fabrice Letertre
Bruce Faure
Christophe Morales
Chrystel Deguet
Original Assignee
Soitec Silicon On Insulator
Commissariat Energie Atomique
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator, Commissariat Energie Atomique filed Critical Soitec Silicon On Insulator
Publication of SG122908A1 publication Critical patent/SG122908A1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Recrystallisation Techniques (AREA)
  • Formation Of Insulating Films (AREA)
  • Chemical Vapour Deposition (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Inorganic Insulating Materials (AREA)
SG200507154A 2004-11-19 2005-11-18 Method for fabricating a germanium on insulator (geoi) type wafer SG122908A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP04292742A EP1659623B1 (fr) 2004-11-19 2004-11-19 Méthode de fabrication d'une plaquette de type germanium sur isolant (GeOI)

Publications (1)

Publication Number Publication Date
SG122908A1 true SG122908A1 (en) 2006-06-29

Family

ID=34931539

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200507154A SG122908A1 (en) 2004-11-19 2005-11-18 Method for fabricating a germanium on insulator (geoi) type wafer

Country Status (9)

Country Link
US (1) US7229898B2 (fr)
EP (2) EP1973155B1 (fr)
JP (1) JP4173884B2 (fr)
KR (1) KR100734239B1 (fr)
CN (1) CN100472709C (fr)
AT (2) ATE392712T1 (fr)
DE (1) DE602004013163T2 (fr)
SG (1) SG122908A1 (fr)
TW (1) TWI297171B (fr)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7538010B2 (en) * 2003-07-24 2009-05-26 S.O.I.Tec Silicon On Insulator Technologies Method of fabricating an epitaxially grown layer
FR2857983B1 (fr) * 2003-07-24 2005-09-02 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiee
US7568412B2 (en) * 2005-10-04 2009-08-04 Marquip, Llc Method for order transition on a plunge slitter
FR2892230B1 (fr) * 2005-10-19 2008-07-04 Soitec Silicon On Insulator Traitement d'une couche de germamium
KR100823031B1 (ko) * 2006-12-21 2008-04-17 동부일렉트로닉스 주식회사 이미지 센서 제조방법
EP1950803B1 (fr) * 2007-01-24 2011-07-27 S.O.I.TEC Silicon on Insulator Technologies S.A. Procédé de fabrication de plaquettes silicium sur isolant, et plaquette correspondante
FR2912552B1 (fr) * 2007-02-14 2009-05-22 Soitec Silicon On Insulator Structure multicouche et son procede de fabrication.
WO2008123116A1 (fr) * 2007-03-26 2008-10-16 Semiconductor Energy Laboratory Co., Ltd. Substrat soi et procédé de réalisation d'un substrat soi
WO2008123117A1 (fr) * 2007-03-26 2008-10-16 Semiconductor Energy Laboratory Co., Ltd. Substrat soi et procédé de réalisation d'un substrat soi
CN101281912B (zh) * 2007-04-03 2013-01-23 株式会社半导体能源研究所 Soi衬底及其制造方法以及半导体装置
CN102623400B (zh) 2007-04-13 2015-05-20 株式会社半导体能源研究所 显示器件、用于制造显示器件的方法、以及soi衬底
EP1986229A1 (fr) * 2007-04-27 2008-10-29 S.O.I.T.E.C. Silicon on Insulator Technologies Procédé de fabrication de galettes de matériau composé et galette de matériau composé correspondante
US20080274626A1 (en) * 2007-05-04 2008-11-06 Frederique Glowacki Method for depositing a high quality silicon dielectric film on a germanium substrate with high quality interface
US8513678B2 (en) 2007-05-18 2013-08-20 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device
FR2923079B1 (fr) * 2007-10-26 2017-10-27 S O I Tec Silicon On Insulator Tech Substrats soi avec couche fine isolante enterree
WO2009057669A1 (fr) * 2007-11-01 2009-05-07 Semiconductor Energy Laboratory Co., Ltd. Procédé de fabrication d'un dispositif de conversion photoélectrique
JP5503876B2 (ja) * 2008-01-24 2014-05-28 株式会社半導体エネルギー研究所 半導体基板の製造方法
US8299485B2 (en) * 2008-03-19 2012-10-30 Soitec Substrates for monolithic optical circuits and electronic circuits
FR2933534B1 (fr) * 2008-07-03 2011-04-01 Soitec Silicon On Insulator Procede de fabrication d'une structure comprenant une couche de germanium sur un substrat
EP2161742A1 (fr) * 2008-09-03 2010-03-10 S.O.I.TEC. Silicon on Insulator Technologies S.A. Procédé pour la fabrication d'un substrat germanium sur un isolateur localement passivé
US8741740B2 (en) * 2008-10-02 2014-06-03 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
FR2968121B1 (fr) 2010-11-30 2012-12-21 Soitec Silicon On Insulator Procede de transfert d'une couche a haute temperature
JP2012156495A (ja) 2011-01-07 2012-08-16 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法
US8786017B2 (en) 2011-03-10 2014-07-22 Tsinghua University Strained Ge-on-insulator structure and method for forming the same
CN102169888B (zh) * 2011-03-10 2012-11-14 清华大学 应变GeOI结构及其形成方法
US8890209B2 (en) * 2011-03-10 2014-11-18 Tsinghua University Strained GE-ON-insulator structure and method for forming the same
US8704306B2 (en) * 2011-03-10 2014-04-22 Tsinghua University Strained Ge-on-insulator structure and method for forming the same
US8802534B2 (en) 2011-06-14 2014-08-12 Semiconductor Energy Laboratory Co., Ltd. Method for forming SOI substrate and apparatus for forming the same
FR2977069B1 (fr) 2011-06-23 2014-02-07 Soitec Silicon On Insulator Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire
CN103832970B (zh) * 2012-11-27 2016-06-15 中国科学院微电子研究所 一种低温晶圆键合方法
KR102279162B1 (ko) * 2015-03-03 2021-07-20 한국전자통신연구원 게르마늄 온 인슐레이터 기판 및 그의 형성방법
KR101889352B1 (ko) 2016-09-13 2018-08-20 한국과학기술연구원 변형된 저마늄을 포함하는 반도체 소자의 제조 방법 및 이에 의해 제조된 반도체 소자
US10763115B2 (en) * 2017-06-16 2020-09-01 Nxp Usa, Inc. Substrate treatment method for semiconductor device fabrication
US10276687B1 (en) * 2017-12-20 2019-04-30 International Business Machines Corporation Formation of self-aligned bottom spacer for vertical transistors
CN114256345A (zh) * 2020-09-21 2022-03-29 上海华力集成电路制造有限公司 一种fdsoi器件结构及其制备方法
CN115070512B (zh) * 2022-03-11 2024-04-26 北京爱瑞思光学仪器有限公司 一种锗晶片的双抛工艺、装置及锗晶片

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681472B1 (fr) 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
US6995430B2 (en) * 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
JP2004335642A (ja) * 2003-05-06 2004-11-25 Canon Inc 基板およびその製造方法
KR20060054387A (ko) * 2003-08-04 2006-05-22 에이에스엠 아메리카, 인코포레이티드 증착 전 게르마늄 표면 처리 방법

Also Published As

Publication number Publication date
ATE515794T1 (de) 2011-07-15
CN1776886A (zh) 2006-05-24
CN100472709C (zh) 2009-03-25
DE602004013163T2 (de) 2009-05-14
TWI297171B (en) 2008-05-21
JP4173884B2 (ja) 2008-10-29
EP1659623A1 (fr) 2006-05-24
EP1659623B1 (fr) 2008-04-16
KR20060056239A (ko) 2006-05-24
EP1973155B1 (fr) 2011-07-06
EP1973155A1 (fr) 2008-09-24
ATE392712T1 (de) 2008-05-15
JP2006148066A (ja) 2006-06-08
US7229898B2 (en) 2007-06-12
DE602004013163D1 (de) 2008-05-29
KR100734239B1 (ko) 2007-07-02
US20060110899A1 (en) 2006-05-25
TW200618047A (en) 2006-06-01

Similar Documents

Publication Publication Date Title
SG122908A1 (en) Method for fabricating a germanium on insulator (geoi) type wafer
SG122972A1 (en) Method for manufacturing compound material wafers
WO2006054024A3 (fr) Amincissement d'une plaquette semiconductrice
ATE441938T1 (de) Herstellungsverfahren für finfets mit verringertem widerstand
TW200739684A (en) Semiconductor device and method for fabricating the same
WO2007142911A3 (fr) Structure semi-conducteur sur isolant réalisée au moyen de recuit par rayonnement
WO2004006311A3 (fr) Transfert d'une couche mince depuis une tranche comprenant une couche tampon
WO2005104192A3 (fr) Procede de fabrication de substrats virtuels lies a une plaquette de gaas/si et de substrats virtuels associes
WO2007127074A3 (fr) Isolant à base de semi-conducteur sur verre fabriqué par un procédé d'amincissement amélioré
WO2005055290A3 (fr) Procede de fabrication d'un substrat semi-conducteur
TW200729343A (en) Method for fabricating controlled stress silicon nitride films
WO2006104529A3 (fr) Zones de jonction de transistor cmos formees par gravure a depot chimique en phase vapeur et sequence de depot
WO2009155122A3 (fr) Empilements et procédés de retraits épitaxiaux
WO2006036753A3 (fr) Procedes et dispositif pour regler un ensemble d'operations de traitement par plasma
WO2007019277A3 (fr) Procede de formation de couches semiconductrices sur des substrats de manipulation
WO2004102635A3 (fr) Procedes de conservation de couches de substrats semi-conducteurs sous contrainte au cours d'un traitement cmos
EP1429381A3 (fr) Procédé de fabrication d'un matériau composé
EP2264755A3 (fr) Procédé de fabrication de plaquettes silicium sur isolant et plaquette correspondante
WO2007126482A3 (fr) Procédés de formation de minces couches d'oxydes sur des tranches semi-conductrices
TW200636822A (en) Structure and method for manufacturing strained silicon directly-on insulator substrate with hybrid crystalling orientation and different stress levels
TW200503101A (en) Method for producing trench isolation structure
EP1577943A3 (fr) Substrat a semi-conducteur et procédé de fabrication associé, et dispositif semi-conducteur
TW200639969A (en) Treatmeny of a removed layer of Si1-yGey
SG159436A1 (en) Method for fabricating a semiconductor on insulator substrate with reduced secco defect density
WO2007133935A3 (fr) Procédé et matériaux pour réguler le profil de dopage dans un matériau pour substrat de circuit intégré