SG125169A1 - Method and apparatus identifying a manufacturing problem area in a layout using a process-sensitivity model - Google Patents

Method and apparatus identifying a manufacturing problem area in a layout using a process-sensitivity model

Info

Publication number
SG125169A1
SG125169A1 SG200508409A SG200508409A SG125169A1 SG 125169 A1 SG125169 A1 SG 125169A1 SG 200508409 A SG200508409 A SG 200508409A SG 200508409 A SG200508409 A SG 200508409A SG 125169 A1 SG125169 A1 SG 125169A1
Authority
SG
Singapore
Prior art keywords
model
target
problem area
sensitivity
layout
Prior art date
Application number
SG200508409A
Other languages
English (en)
Inventor
Lawrence S Melvin Iii
James P Shiely
Original Assignee
Synopsys Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Synopsys Inc filed Critical Synopsys Inc
Publication of SG125169A1 publication Critical patent/SG125169A1/en

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
    • G03F7/705—Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/18—Manufacturability analysis or optimisation for manufacturability
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Electron Beam Exposure (AREA)
SG200508409A 2005-02-24 2005-12-27 Method and apparatus identifying a manufacturing problem area in a layout using a process-sensitivity model SG125169A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/065,409 US7251807B2 (en) 2005-02-24 2005-02-24 Method and apparatus for identifying a manufacturing problem area in a layout using a process-sensitivity model

Publications (1)

Publication Number Publication Date
SG125169A1 true SG125169A1 (en) 2006-09-29

Family

ID=35999476

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200508409A SG125169A1 (en) 2005-02-24 2005-12-27 Method and apparatus identifying a manufacturing problem area in a layout using a process-sensitivity model

Country Status (9)

Country Link
US (4) US7251807B2 (de)
EP (1) EP1696269B1 (de)
JP (1) JP4925408B2 (de)
KR (1) KR101190399B1 (de)
CN (2) CN1828613B (de)
AT (1) ATE442610T1 (de)
DE (1) DE602006009001D1 (de)
SG (1) SG125169A1 (de)
TW (2) TWI325547B (de)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7251807B2 (en) * 2005-02-24 2007-07-31 Synopsys, Inc. Method and apparatus for identifying a manufacturing problem area in a layout using a process-sensitivity model
US7475382B2 (en) * 2005-02-24 2009-01-06 Synopsys, Inc. Method and apparatus for determining an improved assist feature configuration in a mask layout
US7315999B2 (en) * 2005-03-17 2008-01-01 Synopsys, Inc. Method and apparatus for identifying assist feature placement problems
US7496880B2 (en) * 2005-03-17 2009-02-24 Synopsys, Inc. Method and apparatus for assessing the quality of a process model
US7458059B2 (en) * 2005-10-31 2008-11-25 Synopsys, Inc. Model of sensitivity of a simulated layout to a change in original layout, and use of model in proximity correction
US7840287B2 (en) * 2006-04-13 2010-11-23 Fisher-Rosemount Systems, Inc. Robust process model identification in model based control techniques
US7743357B2 (en) * 2006-05-31 2010-06-22 Synopsys, Inc. Method and apparatus for determining a process model that models the impact of CAR/PEB on the resist profile
US7454739B2 (en) 2006-05-31 2008-11-18 Synopsys, Inc. Method and apparatus for determining an accurate photolithography process model
EP1862857B1 (de) * 2006-05-31 2012-08-08 Synopsys, Inc. Verfahren und Vorrichtung zum Bestimmen eines Prozessmodells für die Herstellung integrierter Schaltungen
US20100205573A1 (en) * 2007-07-06 2010-08-12 Sagantiec Israel Ltd. Layout modification engine for modifying a circuit layout comprising fixed and free layout entities
TW200929412A (en) * 2007-12-18 2009-07-01 Airoha Tech Corp Model modification method for a semiconductor device
US8120767B2 (en) * 2008-03-13 2012-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Mask making decision for manufacturing (DFM) on mask quality control
JP2009282319A (ja) * 2008-05-22 2009-12-03 Toshiba Corp パターン検証方法、パターン検証システム、パターン検証プログラム、マスク製造方法、および半導体装置の製造方法
KR101610734B1 (ko) * 2008-06-03 2016-04-08 에이에스엠엘 네델란즈 비.브이. 모델-기반 스캐너 튜닝 방법
US8117568B2 (en) * 2008-09-25 2012-02-14 International Business Machines Corporation Apparatus, method and computer program product for fast simulation of manufacturing effects during integrated circuit design
JP4762288B2 (ja) * 2008-09-26 2011-08-31 株式会社東芝 パターン形成不良領域算出方法
US8181128B2 (en) 2008-10-13 2012-05-15 Synopsys, Inc. Method and apparatus for determining a photolithography process model which models the influence of topography variations
US7954071B2 (en) * 2008-10-31 2011-05-31 Synopsys, Inc. Assist feature placement based on a focus-sensitive cost-covariance field
NL2003718A (en) 2008-11-10 2010-05-11 Brion Tech Inc Methods and system for model-based generic matching and tuning.
US8136054B2 (en) * 2009-01-29 2012-03-13 Synopsys, Inc. Compact abbe's kernel generation using principal component analysis
US8010913B2 (en) * 2009-04-14 2011-08-30 Synopsys, Inc. Model-based assist feature placement using inverse imaging approach
US9448706B2 (en) * 2009-07-29 2016-09-20 Synopsys, Inc. Loop removal in electronic design automation
US8694930B2 (en) * 2011-08-11 2014-04-08 Infineon Technologies Ag Method and apparatus for providing a layout defining a structure to be patterned onto a substrate
US8510699B1 (en) 2012-03-09 2013-08-13 International Business Machines Corporation Performance driven layout optimization using morphing of a basis set of representative layouts
US10365557B2 (en) * 2013-02-24 2019-07-30 Synopsys, Inc. Compact OPC model generation using virtual data
TWI621957B (zh) * 2013-03-14 2018-04-21 新納普系統股份有限公司 使用點擊最佳化的次解析度輔助特徵實現方式
CN103405164B (zh) * 2013-07-23 2015-08-12 山东科技大学 烤箱与烤盘配合布局的方法
JP6346297B2 (ja) * 2014-02-11 2018-06-20 エーエスエムエル ネザーランズ ビー．ブイ． 任意パターンにおける確率的変動を計算するためのモデル
EP2952964A1 (de) * 2014-06-03 2015-12-09 Aselta Nanographics Verfahren zum Bestimmen von Parametern eines IC-Herstellungsverfahrens durch ein differenzielles Verfahren
WO2016008711A1 (en) 2014-07-14 2016-01-21 Asml Netherlands B.V. Optimization of assist features and source
KR102084048B1 (ko) * 2014-10-02 2020-03-03 에이에스엠엘 네델란즈 비.브이. 어시스트 피처들의 규칙-기반 배치
KR102028712B1 (ko) 2015-04-10 2019-10-04 에이에스엠엘 네델란즈 비.브이. 검사와 계측을 위한 방법 및 장치
US10394116B2 (en) 2017-09-06 2019-08-27 International Business Machines Corporation Semiconductor fabrication design rule loophole checking for design for manufacturability optimization
US10621295B2 (en) 2018-04-10 2020-04-14 International Business Machines Corporation Incorporation of process variation contours in design rule and risk estimation aspects of design for manufacturability to increase fabrication yield
CN109596638B (zh) * 2018-10-26 2022-05-06 中国科学院光电研究院 有图形晶圆及掩模版的缺陷检测方法及装置
CN112904662B (zh) * 2021-05-07 2021-07-23 南京晶驱集成电路有限公司 辅助图形的添加方法、装置及测试版图
CN114509912B (zh) * 2022-01-07 2026-04-28 东方晶源微电子科技(北京)股份有限公司 一种掩模优化方法、掩模优化装置及电子设备

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6474547A (en) 1987-09-14 1989-03-20 Motorola Inc Manufacture of semiconductor for compensating strain between pattern on semiconductor body and mask for obtaining pattern
JPH04216548A (ja) * 1990-12-18 1992-08-06 Mitsubishi Electric Corp フォトマスク
JP3223718B2 (ja) * 1994-09-07 2001-10-29 松下電器産業株式会社 マスクデータの作成方法
US5774177A (en) * 1996-09-11 1998-06-30 Milliken Research Corporation Textile fabric inspection system
US5965309A (en) * 1997-08-28 1999-10-12 International Business Machines Corporation Focus or exposure dose parameter control system using tone reversing patterns
US6183919B1 (en) * 1999-06-11 2001-02-06 International Business Machines Corporation Darkfield imaging for enhancing optical detection of edges and minimum features
US6539521B1 (en) * 2000-09-29 2003-03-25 Numerical Technologies, Inc. Dissection of corners in a fabrication layout for correcting proximity effects
US6453457B1 (en) * 2000-09-29 2002-09-17 Numerical Technologies, Inc. Selection of evaluation point locations based on proximity effects model amplitudes for correcting proximity effects in a fabrication layout
AU2002238409A1 (en) * 2000-11-30 2002-06-11 Sigma-C Gmbh Method and device for determining the properties of an integrated circuit
US6873720B2 (en) * 2001-03-20 2005-03-29 Synopsys, Inc. System and method of providing mask defect printability analysis
JP4748343B2 (ja) * 2001-04-26 2011-08-17 大日本印刷株式会社 ウエーハ転写検証方法
TW520544B (en) * 2001-06-15 2003-02-11 United Microelectronics Corp Method and apparatus for measuring bridge caused by mask layout correction
DE10143723B4 (de) * 2001-08-31 2006-09-28 Infineon Technologies Ag Verfahren zur Optimierung eines Layouts für eine Maske zur Verwendung bei der Halbleiterherstellung
US6673638B1 (en) * 2001-11-14 2004-01-06 Kla-Tencor Corporation Method and apparatus for the production of process sensitive lithographic features
US20030121021A1 (en) * 2001-12-26 2003-06-26 Numerical Technologies, Inc. System and method for determining manufacturing error enhancement factor
US6904587B2 (en) * 2002-12-20 2005-06-07 Synopsys, Inc. Incremental lithography mask layout design and verification
US6964032B2 (en) * 2003-02-28 2005-11-08 International Business Machines Corporation Pitch-based subresolution assist feature design
US6934930B2 (en) * 2003-07-08 2005-08-23 Texas Instruments Incorporated Generating an optical model for lens aberrations
JP4684584B2 (ja) * 2003-07-23 2011-05-18 キヤノン株式会社 マスク及びその製造方法、並びに、露光方法
JP2005099765A (ja) * 2003-08-28 2005-04-14 Toshiba Corp プロセス近接効果の予測モデルの作成方法、工程の管理方法、半導体装置の製造方法、フォトマスクの製造方法およびプログラム
US6978438B1 (en) * 2003-10-01 2005-12-20 Advanced Micro Devices, Inc. Optical proximity correction (OPC) technique using generalized figure of merit for photolithograhic processing
US7451068B2 (en) * 2003-10-10 2008-11-11 Synopsys, Inc. Method and apparatus for generating an OPC segmentation based on modeled intensity gradients
US7251807B2 (en) * 2005-02-24 2007-07-31 Synopsys, Inc. Method and apparatus for identifying a manufacturing problem area in a layout using a process-sensitivity model
US7475382B2 (en) * 2005-02-24 2009-01-06 Synopsys, Inc. Method and apparatus for determining an improved assist feature configuration in a mask layout
US7315999B2 (en) * 2005-03-17 2008-01-01 Synopsys, Inc. Method and apparatus for identifying assist feature placement problems

Also Published As

Publication number Publication date
US20060190914A1 (en) 2006-08-24
US7243332B2 (en) 2007-07-10
US7251807B2 (en) 2007-07-31
KR20060094470A (ko) 2006-08-29
EP1696269B1 (de) 2009-09-09
US7784018B2 (en) 2010-08-24
TWI325547B (en) 2010-06-01
KR101190399B1 (ko) 2012-10-12
CN1825323A (zh) 2006-08-30
DE602006009001D1 (de) 2009-10-22
EP1696269A2 (de) 2006-08-30
US7320119B2 (en) 2008-01-15
CN100541498C (zh) 2009-09-16
CN1828613B (zh) 2011-05-18
JP4925408B2 (ja) 2012-04-25
TWI450115B (zh) 2014-08-21
EP1696269A3 (de) 2008-01-23
US20070250804A1 (en) 2007-10-25
TW201017460A (en) 2010-05-01
TW200639668A (en) 2006-11-16
US20060190913A1 (en) 2006-08-24
JP2006235600A (ja) 2006-09-07
ATE442610T1 (de) 2009-09-15
US20060190912A1 (en) 2006-08-24
CN1828613A (zh) 2006-09-06

Similar Documents

Publication Publication Date Title
TW200639668A (en) Method and apparatus for identifying a manufacturing problem area in a layout using a process-sensitivity model
SG125170A1 (en) Method and apparatus for determining an improved assist feature configuration in a mask layout
TW200951672A (en) System and method for modifying a data set of a photomask
TW200632719A (en) Multivariate control of semiconductor processes
DE60334835D1 (de) Vorrichtung und verfahren zur umschaltung zwischen prozessen
SG148015A1 (en) Lithographic apparatus and device manufacturing method
EP1376422A3 (de) System und Vorrichtung zum Risiko-Management in einem Projekt
TW200500498A (en) Method for etching an aluminum layer using an amorphous carbon mask
TWI372426B (en) Method and apparatus for photomask plasma etching
NO20071943L (no) Systemer og fremgangsmater for lavtemperatursgasseparasjon
WO2007092229A3 (en) Transforming metrology data from a semiconductor treatment system using multivariate analysis
GB0507205D0 (en) System, method and apparatus for restricting matching of automated trades
SG143183A1 (en) A method , program product and apparatus for performing decomposition of a pattern for use in a dpt process
WO2008121955A3 (en) In-line lithography and etch system
ATE499315T1 (de) Verfahren zum singulieren von ophthalmischer linsen
DE602006012292D1 (de) Verfahren zur datenverarbeitung mit modularer potenzierung und dazugehörige vorrichtung
TW200617610A (en) Pattern data producing method, pattern verification method, photo mask producing method, and semiconductor device manufacturing method
TW200725695A (en) Method for manufacturing semiconductor device
PL1591557T3 (pl) Sposób nakładania powłok za pomocą urządzeń pracujących w linii ciągłej
SG155256A1 (en) Immersion liquid, exposure apparatus, and exposure process
GB2489859A (en) Through silicon via lithographic alignment and registration
WO2007041602A8 (en) Lithography verification using guard bands
TW200638462A (en) System and method for manufacturing a mask for semiconductor processing
SG129405A1 (en) Manufacturing method for electronic substrate, manufacturing method for electro-optical device, and manufacturing method for electronic device
TW200703537A (en) Substrate processing apparatus and substrate housing method