SG34348A1 - Multilayered A1-alloy structure for metal conductors - Google Patents

Multilayered A1-alloy structure for metal conductors

Info

Publication number
SG34348A1
SG34348A1 SG1995002386A SG1995002386A SG34348A1 SG 34348 A1 SG34348 A1 SG 34348A1 SG 1995002386 A SG1995002386 A SG 1995002386A SG 1995002386 A SG1995002386 A SG 1995002386A SG 34348 A1 SG34348 A1 SG 34348A1
Authority
SG
Singapore
Prior art keywords
multilayered
alloy structure
metal conductors
conductors
alloy
Prior art date
Application number
SG1995002386A
Other languages
English (en)
Inventor
Cheryl A Bollinger
Edward A Dein
Sailesh Mansinh Merchant
Arun Kumar Nanda
Pradip Kumar Roy
Cletus Walter Wilkins Jr
Original Assignee
At & T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by At & T Corp filed Critical At & T Corp
Publication of SG34348A1 publication Critical patent/SG34348A1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
SG1995002386A 1994-12-29 1995-12-28 Multilayered A1-alloy structure for metal conductors SG34348A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/365,652 US5561083A (en) 1994-12-29 1994-12-29 Method of making multilayered Al-alloy structure for metal conductors

Publications (1)

Publication Number Publication Date
SG34348A1 true SG34348A1 (en) 1996-12-06

Family

ID=23439761

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1995002386A SG34348A1 (en) 1994-12-29 1995-12-28 Multilayered A1-alloy structure for metal conductors

Country Status (6)

Country Link
US (2) US5561083A (de)
EP (1) EP0720231A3 (de)
JP (1) JP3296708B2 (de)
KR (1) KR960026410A (de)
SG (1) SG34348A1 (de)
TW (1) TW298675B (de)

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TW520072U (en) * 1991-07-08 2003-02-01 Samsung Electronics Co Ltd A semiconductor device having a multi-layer metal contact
JP3744980B2 (ja) * 1995-07-27 2006-02-15 株式会社半導体エネルギー研究所 半導体装置
SG55246A1 (en) * 1995-12-29 1998-12-21 Ibm Aluminum alloy for the damascene process for on-chip wiring applications
US5663108A (en) * 1996-06-13 1997-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Optimized metal pillar via process
JPH1027797A (ja) * 1996-07-10 1998-01-27 Oki Electric Ind Co Ltd Ａｌ／Ｔｉ積層配線およびその形成方法
KR100415095B1 (ko) * 1996-11-27 2004-03-31 주식회사 하이닉스반도체 반도체소자의제조방법
US5943601A (en) * 1997-04-30 1999-08-24 International Business Machines Corporation Process for fabricating a metallization structure
DE19734434C1 (de) * 1997-08-08 1998-12-10 Siemens Ag Halbleiterkörper mit Rückseitenmetallisierung und Verfahren zu deren Herstellung
JP3500308B2 (ja) 1997-08-13 2004-02-23 インターナショナル・ビジネス・マシーンズ・コーポレーション 集積回路
US6255688B1 (en) * 1997-11-21 2001-07-03 Agere Systems Guardian Corp. Capacitor having aluminum alloy bottom plate
US6380627B1 (en) * 1998-06-26 2002-04-30 The Regents Of The University Of California Low resistance barrier layer for isolating, adhering, and passivating copper metal in semiconductor fabrication
US6100195A (en) 1998-12-28 2000-08-08 Chartered Semiconductor Manu. Ltd. Passivation of copper interconnect surfaces with a passivating metal layer
US6320265B1 (en) * 1999-04-12 2001-11-20 Lucent Technologies Inc. Semiconductor device with high-temperature ohmic contact and method of forming the same
US7230316B2 (en) 2002-12-27 2007-06-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having transferred integrated circuit
US7628309B1 (en) * 2005-05-03 2009-12-08 Rosemount Aerospace Inc. Transient liquid phase eutectic bonding
US7400042B2 (en) * 2005-05-03 2008-07-15 Rosemount Aerospace Inc. Substrate with adhesive bonding metallization with diffusion barrier
US20070013014A1 (en) * 2005-05-03 2007-01-18 Shuwen Guo High temperature resistant solid state pressure sensor
US7538401B2 (en) 2005-05-03 2009-05-26 Rosemount Aerospace Inc. Transducer for use in harsh environments
DE102016101801B4 (de) * 2016-02-02 2021-01-14 Infineon Technologies Ag Lastanschluss eines leistungshalbleiterbauelements, leistungshalbleitermodul damit und herstellungsverfahren dafür
KR20190001445U (ko) 2017-12-08 2019-06-18 최재양 삽입식 샤워기 홀더

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55132056A (en) * 1979-04-03 1980-10-14 Toshiba Corp Semiconductor device
US4373966A (en) * 1981-04-30 1983-02-15 International Business Machines Corporation Forming Schottky barrier diodes by depositing aluminum silicon and copper or binary alloys thereof and alloy-sintering
US4517225A (en) * 1983-05-02 1985-05-14 Signetics Corporation Method for manufacturing an electrical interconnection by selective tungsten deposition
US4673623A (en) * 1985-05-06 1987-06-16 The Board Of Trustees Of The Leland Stanford Junior University Layered and homogeneous films of aluminum and aluminum/silicon with titanium and tungsten for multilevel interconnects
US4910580A (en) * 1987-08-27 1990-03-20 Siemens Aktiengesellschaft Method for manufacturing a low-impedance, planar metallization composed of aluminum or of an aluminum alloy
US4987562A (en) * 1987-08-28 1991-01-22 Fujitsu Limited Semiconductor layer structure having an aluminum-silicon alloy layer
JPH01185948A (ja) * 1988-01-21 1989-07-25 Seiko Epson Corp 半導体装置
KR920005701B1 (ko) * 1989-07-20 1992-07-13 현대전자산업 주식회사 반도체 집적회로 내의 소자 연결용 금속배선층 및 그 제조방법
JPH04363024A (ja) * 1990-11-30 1992-12-15 Toshiba Corp 半導体装置の製造方法
US5345108A (en) * 1991-02-26 1994-09-06 Nec Corporation Semiconductor device having multi-layer electrode wiring
DE4200809C2 (de) * 1991-03-20 1996-12-12 Samsung Electronics Co Ltd Verfahren zur Bildung einer metallischen Verdrahtungsschicht in einem Halbleiterbauelement
KR940004256B1 (en) * 1991-04-09 1994-05-19 Samsung Electronics Co Ltd Making method of semiconductor device
TW520072U (en) * 1991-07-08 2003-02-01 Samsung Electronics Co Ltd A semiconductor device having a multi-layer metal contact
FR2678818B1 (fr) * 1991-07-11 1995-07-13 Olivier Ets Georges Dispositif arrache-fils pour semelle de suceur d'aspirateur.
KR960010056B1 (ko) * 1992-12-10 1996-07-25 삼성전자 주식회사 반도체장치 및 그 제조 방법
US5427666A (en) * 1993-09-09 1995-06-27 Applied Materials, Inc. Method for in-situ cleaning a Ti target in a Ti + TiN coating process
US5360995A (en) * 1993-09-14 1994-11-01 Texas Instruments Incorporated Buffered capped interconnect for a semiconductor device
US5444022A (en) * 1993-12-29 1995-08-22 Intel Corporation Method of fabricating an interconnection structure for an integrated circuit
US5523259A (en) * 1994-12-05 1996-06-04 At&T Corp. Method of forming metal layers formed as a composite of sub-layers using Ti texture control layer

Also Published As

Publication number Publication date
EP0720231A3 (de) 1996-12-11
JPH08236707A (ja) 1996-09-13
JP3296708B2 (ja) 2002-07-02
US5561083A (en) 1996-10-01
US5641994A (en) 1997-06-24
TW298675B (de) 1997-02-21
KR960026410A (ko) 1996-07-22
EP0720231A2 (de) 1996-07-03

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