SG54593A1 - Method of manufacturing semiconductor article - Google Patents

Method of manufacturing semiconductor article

Info

Publication number
SG54593A1
SG54593A1 SG1997004024A SG1997004024A SG54593A1 SG 54593 A1 SG54593 A1 SG 54593A1 SG 1997004024 A SG1997004024 A SG 1997004024A SG 1997004024 A SG1997004024 A SG 1997004024A SG 54593 A1 SG54593 A1 SG 54593A1
Authority
SG
Singapore
Prior art keywords
substrate
porous silicon
silicon layer
image
multilayer structure
Prior art date
Application number
SG1997004024A
Other languages
English (en)
Inventor
Kiyofumi Sakaguchi
Takao Yonehara
Tadashi Atoji
Original Assignee
Canon Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Kk filed Critical Canon Kk
Publication of SG54593A1 publication Critical patent/SG54593A1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1924—Preparing SOI wafers with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Recrystallisation Techniques (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Element Separation (AREA)
SG1997004024A 1996-11-15 1997-11-12 Method of manufacturing semiconductor article SG54593A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30453996 1996-11-15

Publications (1)

Publication Number Publication Date
SG54593A1 true SG54593A1 (en) 1998-11-16

Family

ID=17934226

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1997004024A SG54593A1 (en) 1996-11-15 1997-11-12 Method of manufacturing semiconductor article

Country Status (10)

Country Link
EP (1) EP0843346B1 (de)
KR (1) KR100279756B1 (de)
CN (1) CN1104036C (de)
AT (1) ATE266258T1 (de)
AU (1) AU745315B2 (de)
CA (1) CA2220600C (de)
DE (1) DE69728950T2 (de)
MY (1) MY114469A (de)
SG (1) SG54593A1 (de)
TW (1) TW372366B (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE275761T1 (de) * 1997-03-26 2004-09-15 Canon Kk Halbleitersubstrat und verfahren zu dessen herstellung
SG71094A1 (en) * 1997-03-26 2000-03-21 Canon Kk Thin film formation using laser beam heating to separate layers
JP3492142B2 (ja) * 1997-03-27 2004-02-03 キヤノン株式会社 半導体基材の製造方法
TW522488B (en) 1998-07-27 2003-03-01 Canon Kk Sample processing apparatus and method
JP2000349264A (ja) 1998-12-04 2000-12-15 Canon Inc 半導体ウエハの製造方法、使用方法および利用方法
EP1039513A3 (de) * 1999-03-26 2008-11-26 Canon Kabushiki Kaisha Verfahren zur Herstellung einer SOI-Scheibe
DE19940512A1 (de) * 1999-08-26 2001-03-22 Bosch Gmbh Robert Verfahren zur Verkappung eines Bauelementes mit einer Kavernenstruktur und Verfahren zur Herstellung der Kavernenstruktur
CN1119830C (zh) * 2000-04-27 2003-08-27 中国科学院上海冶金研究所 一种器件转移方法
US6420243B1 (en) * 2000-12-04 2002-07-16 Motorola, Inc. Method for producing SOI wafers by delamination
KR20040007852A (ko) * 2002-07-11 2004-01-28 (주)두진리사이클 백업보드의 금속막 박리방법 및 이를 수행하는 장치
EP1482548B1 (de) 2003-05-26 2016-04-13 Soitec Verfahren zur Herstellung von Halbleiterscheiben
JP4348454B2 (ja) * 2007-11-08 2009-10-21 三菱重工業株式会社 デバイスおよびデバイス製造方法
TW201133945A (en) * 2010-01-12 2011-10-01 jian-min Song Diamond LED devices and associated methods
CN101789466B (zh) * 2010-02-10 2011-12-07 上海理工大学 太阳能电池制作方法
FR2984007B1 (fr) * 2011-12-13 2015-05-08 Soitec Silicon On Insulator Procede de stabilisation d'une interface de collage situee au sein d'une structure comprenant une couche d'oxyde enterree et structure obtenue
FR2984597B1 (fr) * 2011-12-20 2016-07-29 Commissariat Energie Atomique Fabrication d’une structure souple par transfert de couches
EP2817819A4 (de) 2012-02-26 2015-09-02 Solexel Inc Systeme und verfahren zur laserteilung und vorrichtungsschichtübertragung
CN106992140A (zh) * 2016-01-20 2017-07-28 沈阳硅基科技有限公司 一种采用激光裂片技术制备soi硅片的方法
US20180068886A1 (en) * 2016-09-02 2018-03-08 Qualcomm Incorporated Porous semiconductor layer transfer for an integrated circuit structure
JP6834932B2 (ja) * 2017-12-19 2021-02-24 株式会社Sumco 貼り合わせウェーハ用の支持基板の製造方法および貼り合わせウェーハの製造方法
FR3079532B1 (fr) 2018-03-28 2022-03-25 Soitec Silicon On Insulator Procede de fabrication d'une couche monocristalline de materiau ain et substrat pour croissance par epitaxie d'une couche monocristalline de materiau ain
CN109904065B (zh) * 2019-02-21 2021-05-11 中国科学院上海微系统与信息技术研究所 异质结构的制备方法
CN116918031A (zh) * 2021-03-01 2023-10-20 尤米科尔公司 化合物半导体层状结构及其制备方法
GB202213149D0 (en) * 2022-09-08 2022-10-26 Poro Tech Ltd Method of separating a semiconductor device from a substrate
CN117690943B (zh) * 2024-01-31 2024-06-04 合肥晶合集成电路股份有限公司 一种图像传感器的制作方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH032889A (ja) * 1989-05-31 1991-01-09 Seikosha Co Ltd 表示装置
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JP3293736B2 (ja) * 1996-02-28 2002-06-17 キヤノン株式会社 半導体基板の作製方法および貼り合わせ基体
JP3257580B2 (ja) * 1994-03-10 2002-02-18 キヤノン株式会社 半導体基板の作製方法

Also Published As

Publication number Publication date
CN1104036C (zh) 2003-03-26
EP0843346A2 (de) 1998-05-20
KR19980042472A (ko) 1998-08-17
KR100279756B1 (ko) 2001-03-02
TW372366B (en) 1999-10-21
EP0843346A3 (de) 1998-07-08
DE69728950D1 (de) 2004-06-09
EP0843346B1 (de) 2004-05-06
AU4517497A (en) 1998-05-21
CA2220600C (en) 2002-02-12
MY114469A (en) 2002-10-31
DE69728950T2 (de) 2005-03-31
ATE266258T1 (de) 2004-05-15
CA2220600A1 (en) 1998-05-15
AU745315B2 (en) 2002-03-21
CN1191383A (zh) 1998-08-26

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