SG74095A1 - Isolation trench fabrication process - Google Patents

Isolation trench fabrication process

Info

Publication number
SG74095A1
SG74095A1 SG9804384A SG1998004384A SG74095A1 SG 74095 A1 SG74095 A1 SG 74095A1 SG 9804384 A SG9804384 A SG 9804384A SG 1998004384 A SG1998004384 A SG 1998004384A SG 74095 A1 SG74095 A1 SG 74095A1
Authority
SG
Singapore
Prior art keywords
fabrication process
isolation trench
trench fabrication
isolation
trench
Prior art date
Application number
SG9804384A
Other languages
English (en)
Inventor
Xu Jim-Jun
Haddad Homayoon
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Publication of SG74095A1 publication Critical patent/SG74095A1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/06—Planarisation of inorganic insulating materials
    • H10P95/062—Planarisation of inorganic insulating materials involving a dielectric removal step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0143—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising concurrently refilling multiple trenches having different shapes or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0145—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape
SG9804384A 1998-04-30 1998-10-30 Isolation trench fabrication process SG74095A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/071,051 US6033961A (en) 1998-04-30 1998-04-30 Isolation trench fabrication process

Publications (1)

Publication Number Publication Date
SG74095A1 true SG74095A1 (en) 2001-05-22

Family

ID=22098939

Family Applications (1)

Application Number Title Priority Date Filing Date
SG9804384A SG74095A1 (en) 1998-04-30 1998-10-30 Isolation trench fabrication process

Country Status (5)

Country Link
US (1) US6033961A (da)
EP (1) EP0954023A1 (da)
JP (1) JPH11330228A (da)
KR (1) KR100613939B1 (da)
SG (1) SG74095A1 (da)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7157385B2 (en) * 2003-09-05 2007-01-02 Micron Technology, Inc. Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuitry
EP0929098A1 (en) * 1998-01-13 1999-07-14 STMicroelectronics S.r.l. Process for selectively implanting dopants into the bottom of a deep trench
US6528389B1 (en) * 1998-12-17 2003-03-04 Lsi Logic Corporation Substrate planarization with a chemical mechanical polishing stop layer
US6284560B1 (en) * 1998-12-18 2001-09-04 Eastman Kodak Company Method for producing co-planar surface structures
US6300219B1 (en) * 1999-08-30 2001-10-09 Micron Technology, Inc. Method of forming trench isolation regions
US6849518B2 (en) * 2002-05-07 2005-02-01 Intel Corporation Dual trench isolation using single critical lithographic patterning
US7125815B2 (en) * 2003-07-07 2006-10-24 Micron Technology, Inc. Methods of forming a phosphorous doped silicon dioxide comprising layer
US7053010B2 (en) * 2004-03-22 2006-05-30 Micron Technology, Inc. Methods of depositing silicon dioxide comprising layers in the fabrication of integrated circuitry, methods of forming trench isolation, and methods of forming arrays of memory cells
US7235459B2 (en) 2004-08-31 2007-06-26 Micron Technology, Inc. Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry
US7217634B2 (en) * 2005-02-17 2007-05-15 Micron Technology, Inc. Methods of forming integrated circuitry
US7510966B2 (en) * 2005-03-07 2009-03-31 Micron Technology, Inc. Electrically conductive line, method of forming an electrically conductive line, and method of reducing titanium silicide agglomeration in fabrication of titanium silicide over polysilicon transistor gate lines
US8012847B2 (en) * 2005-04-01 2011-09-06 Micron Technology, Inc. Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating integrated circuitry
US8105956B2 (en) * 2009-10-20 2012-01-31 Micron Technology, Inc. Methods of forming silicon oxides and methods of forming interlevel dielectrics
CN104103571B (zh) * 2013-04-15 2017-06-09 中芯国际集成电路制造(上海)有限公司 浅沟槽隔离结构的形成方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5665202A (en) * 1995-11-24 1997-09-09 Motorola, Inc. Multi-step planarization process using polishing at two different pad pressures
JPH1022374A (ja) * 1996-07-08 1998-01-23 Fujitsu Ltd 半導体装置の製造方法
US5712185A (en) * 1996-04-23 1998-01-27 United Microelectronics Method for forming shallow trench isolation
US5721172A (en) * 1996-12-02 1998-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned polish stop layer hard masking method for forming planarized aperture fill layers
US5728621A (en) * 1997-04-28 1998-03-17 Chartered Semiconductor Manufacturing Pte Ltd Method for shallow trench isolation
US5817567A (en) * 1997-04-07 1998-10-06 Taiwan Semiconductor Manufacturing Company Ltd. Shallow trench isolation method

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5229316A (en) * 1992-04-16 1993-07-20 Micron Technology, Inc. Semiconductor processing method for forming substrate isolation trenches
US5933748A (en) * 1996-01-22 1999-08-03 United Microelectronics Corp. Shallow trench isolation process
KR100213196B1 (ko) * 1996-03-15 1999-08-02 윤종용 트렌치 소자분리
US5926713A (en) * 1996-04-17 1999-07-20 Advanced Micro Devices, Inc. Method for achieving global planarization by forming minimum mesas in large field areas
US5923992A (en) * 1997-02-11 1999-07-13 Advanced Micro Devices, Inc. Integrated circuit formed with shallow isolation structures having nitride placed on the trench dielectric
US5930644A (en) * 1997-07-23 1999-07-27 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming a shallow trench isolation using oxide slope etching
US5945352A (en) * 1997-12-19 1999-08-31 Advanced Micro Devices Method for fabrication of shallow isolation trenches with sloped wall profiles

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5665202A (en) * 1995-11-24 1997-09-09 Motorola, Inc. Multi-step planarization process using polishing at two different pad pressures
US5712185A (en) * 1996-04-23 1998-01-27 United Microelectronics Method for forming shallow trench isolation
JPH1022374A (ja) * 1996-07-08 1998-01-23 Fujitsu Ltd 半導体装置の製造方法
US5721172A (en) * 1996-12-02 1998-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned polish stop layer hard masking method for forming planarized aperture fill layers
US5817567A (en) * 1997-04-07 1998-10-06 Taiwan Semiconductor Manufacturing Company Ltd. Shallow trench isolation method
US5728621A (en) * 1997-04-28 1998-03-17 Chartered Semiconductor Manufacturing Pte Ltd Method for shallow trench isolation

Also Published As

Publication number Publication date
US6033961A (en) 2000-03-07
EP0954023A1 (en) 1999-11-03
KR100613939B1 (ko) 2006-08-18
JPH11330228A (ja) 1999-11-30
KR19990083587A (ko) 1999-11-25

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