SG82620A1 - Method and apparatus for processing resin sealed lead frame - Google Patents

Method and apparatus for processing resin sealed lead frame

Info

Publication number
SG82620A1
SG82620A1 SG9903152A SG1999003152A SG82620A1 SG 82620 A1 SG82620 A1 SG 82620A1 SG 9903152 A SG9903152 A SG 9903152A SG 1999003152 A SG1999003152 A SG 1999003152A SG 82620 A1 SG82620 A1 SG 82620A1
Authority
SG
Singapore
Prior art keywords
lead frame
sealed lead
resin sealed
processing resin
processing
Prior art date
Application number
SG9903152A
Other languages
English (en)
Inventor
Osada Michio
Hidaka Tetsuo
Horiuchi Kazuo
Original Assignee
Towa Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP10219613A external-priority patent/JP2000036555A/ja
Priority claimed from JP10331117A external-priority patent/JP2000156449A/ja
Application filed by Towa Corp filed Critical Towa Corp
Publication of SG82620A1 publication Critical patent/SG82620A1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/04—Manufacture or treatment of leadframes
    • H10W70/048—Mechanical treatments, e.g. punching, cutting, deforming or cold welding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/907—Continuous processing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/907—Continuous processing
    • Y10S438/908—Utilizing cluster apparatus
SG9903152A 1998-07-17 1999-07-02 Method and apparatus for processing resin sealed lead frame SG82620A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP10219613A JP2000036555A (ja) 1998-07-17 1998-07-17 樹脂封止済リードフレームの加工方法及び装置
JP10331117A JP2000156449A (ja) 1998-11-20 1998-11-20 樹脂封止済リードフレームの加工方法及び装置

Publications (1)

Publication Number Publication Date
SG82620A1 true SG82620A1 (en) 2001-08-21

Family

ID=26523241

Family Applications (1)

Application Number Title Priority Date Filing Date
SG9903152A SG82620A1 (en) 1998-07-17 1999-07-02 Method and apparatus for processing resin sealed lead frame

Country Status (6)

Country Link
US (2) US6258628B1 (fr)
EP (1) EP0973192A3 (fr)
KR (1) KR100345262B1 (fr)
MY (1) MY120818A (fr)
SG (1) SG82620A1 (fr)
TW (1) TW486797B (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG82620A1 (en) * 1998-07-17 2001-08-21 Towa Corp Method and apparatus for processing resin sealed lead frame
NL1018510C2 (nl) * 2001-07-11 2003-01-14 Fico Bv Werkwijze en inrichting voor het bewerken van een band met elektronische componenten en band met elektronische componenten.
JP4079874B2 (ja) * 2003-12-25 2008-04-23 沖電気工業株式会社 半導体装置の製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5332405A (en) * 1992-09-01 1994-07-26 Golomb Mark S Apparatus for manufacturing semiconductor lead frames in a circular path
US5361486A (en) * 1990-09-11 1994-11-08 Asm-Fico Tooling B.V. System of machining devices

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6074552A (ja) * 1983-09-30 1985-04-26 Fujitsu Ltd ダムリ−ド切断方法及び切断装置
KR910001118B1 (ko) * 1985-11-13 1991-02-23 후지쓰 가부시끼가이샤 Ic 시이트 절단 프레스 및 이를 이용한 ic 시이트 가공장치
JP3174115B2 (ja) 1991-12-20 2001-06-11 株式会社放電精密加工研究所 順送り加工装置用カセット交換装置
JP2790085B2 (ja) * 1995-07-26 1998-08-27 日本電気株式会社 半導体装置の製造方法及び製造装置
SG82620A1 (en) * 1998-07-17 2001-08-21 Towa Corp Method and apparatus for processing resin sealed lead frame

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5361486A (en) * 1990-09-11 1994-11-08 Asm-Fico Tooling B.V. System of machining devices
US5332405A (en) * 1992-09-01 1994-07-26 Golomb Mark S Apparatus for manufacturing semiconductor lead frames in a circular path

Also Published As

Publication number Publication date
KR100345262B1 (ko) 2002-07-19
TW486797B (en) 2002-05-11
US20010021409A1 (en) 2001-09-13
US6258628B1 (en) 2001-07-10
EP0973192A3 (fr) 2002-05-08
MY120818A (en) 2005-11-30
KR20000011794A (ko) 2000-02-25
EP0973192A2 (fr) 2000-01-19

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