SG87811A1 - Integration on bipolar and cmos devices for sub-0.1 micrometer transistors - Google Patents

Integration on bipolar and cmos devices for sub-0.1 micrometer transistors

Info

Publication number
SG87811A1
SG87811A1 SG9902997A SG1999002997A SG87811A1 SG 87811 A1 SG87811 A1 SG 87811A1 SG 9902997 A SG9902997 A SG 9902997A SG 1999002997 A SG1999002997 A SG 1999002997A SG 87811 A1 SG87811 A1 SG 87811A1
Authority
SG
Singapore
Prior art keywords
emitter
substrate
mask
oxide layer
polysilicon layer
Prior art date
Application number
SG9902997A
Other languages
English (en)
Inventor
Pan Yang
Er Zhuang Liu
Original Assignee
Chartered Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chartered Semiconductor Mfg filed Critical Chartered Semiconductor Mfg
Publication of SG87811A1 publication Critical patent/SG87811A1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
SG9902997A 1999-02-18 1999-06-21 Integration on bipolar and cmos devices for sub-0.1 micrometer transistors SG87811A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/252,626 US6284581B1 (en) 1999-02-18 1999-02-18 Integration of bipolar and CMOS devices for sub-0.1 micrometer transistors

Publications (1)

Publication Number Publication Date
SG87811A1 true SG87811A1 (en) 2002-04-16

Family

ID=22956834

Family Applications (1)

Application Number Title Priority Date Filing Date
SG9902997A SG87811A1 (en) 1999-02-18 1999-06-21 Integration on bipolar and cmos devices for sub-0.1 micrometer transistors

Country Status (6)

Country Link
US (2) US6284581B1 (de)
EP (1) EP1030363B1 (de)
JP (1) JP2000243859A (de)
AT (1) ATE373318T1 (de)
DE (1) DE69937098T2 (de)
SG (1) SG87811A1 (de)

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US6211562B1 (en) * 1999-02-24 2001-04-03 Micron Technology, Inc. Homojunction semiconductor devices with low barrier tunnel oxide contacts
JP2001085463A (ja) * 1999-09-09 2001-03-30 Rohm Co Ltd 半導体チップおよびそれを用いた半導体装置
US6555874B1 (en) * 2000-08-28 2003-04-29 Sharp Laboratories Of America, Inc. Method of fabricating high performance SiGe heterojunction bipolar transistor BiCMOS on a silicon-on-insulator substrate
US6894366B2 (en) * 2000-10-10 2005-05-17 Texas Instruments Incorporated Bipolar junction transistor with a counterdoped collector region
US6790722B1 (en) * 2000-11-22 2004-09-14 International Business Machines Corporation Logic SOI structure, process and application for vertical bipolar transistor
US6699741B1 (en) * 2002-08-16 2004-03-02 National Semiconductor Corporation Single poly bipolar transistor and method that uses a selectively epitaxially grown highly-boron-doped silicon layer as a diffusion source for an extrinsic base region
US20040105202A1 (en) * 2002-12-03 2004-06-03 Industrial Technology Research Institute Electrostatic discharge protection device and method using depletion switch
US6730610B1 (en) * 2002-12-20 2004-05-04 Taiwan Semiconductor Manufacturing Co., Ltd Multiple thickness hard mask method for optimizing laterally adjacent patterned layer linewidths
KR100608352B1 (ko) * 2003-03-05 2006-08-09 주식회사 하이닉스반도체 반도체소자의 제조방법
KR100596880B1 (ko) * 2004-09-01 2006-07-05 동부일렉트로닉스 주식회사 반도체 소자의 게이트 형성 방법
DE102007034801B4 (de) * 2007-03-26 2010-10-28 X-Fab Semiconductor Foundries Ag BiMOS-Halbleiterbauelement mit Herstellverfahren mit Bipolarintegration ohne zusätzliche Maskenschritte
US9520486B2 (en) 2009-11-04 2016-12-13 Analog Devices, Inc. Electrostatic protection device
CN102376775B (zh) * 2010-08-26 2014-04-16 上海华虹宏力半导体制造有限公司 BiCMOS工艺中的寄生PIN器件及制造方法
CN102386183B (zh) * 2010-08-31 2014-04-16 上海华虹宏力半导体制造有限公司 BiCMOS工艺中的寄生PIN器件组合结构及制造方法
US10199482B2 (en) * 2010-11-29 2019-02-05 Analog Devices, Inc. Apparatus for electrostatic discharge protection
US8709894B2 (en) * 2011-09-16 2014-04-29 Micron Technology, Inc. 3D structured memory devices and methods for manufacturing thereof
US9087917B2 (en) * 2013-09-10 2015-07-21 Texas Instruments Incorporated Inner L-spacer for replacement gate flow
CN105336681B (zh) * 2014-07-28 2018-05-04 中芯国际集成电路制造(上海)有限公司 半导体器件的制作方法及半导体器件
US9484739B2 (en) 2014-09-25 2016-11-01 Analog Devices Global Overvoltage protection device and method
US10181719B2 (en) 2015-03-16 2019-01-15 Analog Devices Global Overvoltage blocking protection device
CN108346659B (zh) * 2017-01-23 2021-02-23 中芯国际集成电路制造(上海)有限公司 一种可编程存储单元及电子装置
GB2561388B (en) 2017-04-13 2019-11-06 Raytheon Systems Ltd Silicon carbide integrated circuit
US10290631B2 (en) * 2017-05-05 2019-05-14 Newport Fab, Llc Linearity and lateral isolation in a BiCMOS process through counter-doping of epitaxial silicon region
US10319716B2 (en) * 2017-05-05 2019-06-11 Newport Fab, Llc Substrate isolation for low-loss radio frequency (RF) circuits
KR102845847B1 (ko) 2019-09-20 2025-08-14 삼성전자주식회사 반도체 장치

Citations (3)

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US4755487A (en) * 1985-09-21 1988-07-05 Stc Plc Method for making bipolar transistors using rapid thermal annealing
US4902639A (en) * 1989-08-03 1990-02-20 Motorola, Inc. Process for making BiCMOS integrated circuit having a shallow trench bipolar transistor with vertical base contacts
US5338696A (en) * 1990-04-02 1994-08-16 National Semiconductor Corporation Method of fabricating BiCMOS device

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US3966577A (en) * 1973-08-27 1976-06-29 Trw Inc. Dielectrically isolated semiconductor devices
US5148255A (en) * 1985-09-25 1992-09-15 Hitachi, Ltd. Semiconductor memory device
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US5065208A (en) * 1987-01-30 1991-11-12 Texas Instruments Incorporated Integrated bipolar and CMOS transistor with titanium nitride interconnections
KR930010116B1 (ko) * 1990-10-22 1993-10-14 한국전기통신공사 BiCMOS 소자의 제조방법
US5696006A (en) * 1992-06-24 1997-12-09 Matsushita Electric Industrial Co., Ltd. Method of manufacturing Bi-MOS device
US5504362A (en) 1992-12-22 1996-04-02 International Business Machines Corporation Electrostatic discharge protection device
EP0613181A1 (de) 1993-02-26 1994-08-31 STMicroelectronics S.r.l. CMOS-Prozess kompatibler Bipolar-Transistor
JP3273681B2 (ja) * 1993-12-16 2002-04-08 三菱電機株式会社 半導体装置の製造方法
JPH07176639A (ja) 1993-12-17 1995-07-14 Nec Corp 半導体集積回路装置及びその製造方法
US5439833A (en) * 1994-03-15 1995-08-08 National Semiconductor Corp. Method of making truly complementary and self-aligned bipolar and CMOS transistor structures with minimized base and gate resistances and parasitic capacitance
JP3545470B2 (ja) * 1994-12-01 2004-07-21 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
JP3006825B2 (ja) 1995-03-30 2000-02-07 日本電気株式会社 半導体集積回路装置の製造方法
US5606202A (en) * 1995-04-25 1997-02-25 International Business Machines, Corporation Planarized gate conductor on substrates with above-surface isolation
JP3400181B2 (ja) * 1995-04-25 2003-04-28 ローム株式会社 半導体装置およびその製造方法
US5990507A (en) * 1996-07-09 1999-11-23 Kabushiki Kaisha Toshiba Semiconductor device having ferroelectric capacitor structures
US5681765A (en) 1996-10-28 1997-10-28 National Semiconductor Corporation Process for fabricating single polysilicon high performance BICMOS
JP3077742B2 (ja) * 1997-03-03 2000-08-14 日本電気株式会社 半導体装置及びその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4755487A (en) * 1985-09-21 1988-07-05 Stc Plc Method for making bipolar transistors using rapid thermal annealing
US4902639A (en) * 1989-08-03 1990-02-20 Motorola, Inc. Process for making BiCMOS integrated circuit having a shallow trench bipolar transistor with vertical base contacts
US5338696A (en) * 1990-04-02 1994-08-16 National Semiconductor Corporation Method of fabricating BiCMOS device

Also Published As

Publication number Publication date
US6284581B1 (en) 2001-09-04
ATE373318T1 (de) 2007-09-15
DE69937098T2 (de) 2008-06-19
JP2000243859A (ja) 2000-09-08
US6649982B2 (en) 2003-11-18
EP1030363B1 (de) 2007-09-12
EP1030363A2 (de) 2000-08-23
US20010031521A1 (en) 2001-10-18
DE69937098D1 (de) 2007-10-25
EP1030363A3 (de) 2004-06-16

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