SU1069166A2 - Two-level optoelectronic switch - Google Patents

Abstract

TWO-RELATED OPTOEJKTRON Hbdt PERBKJIAATBL on author. St. M 951706, characterized in that, in order to simplify the setting during operation and to ensure the reliability of the switch, a memory block, a bit key, a sampling block, the first input of which is combined with the first input of the first sampling unit, are added to it, the second input is connected to the output of the second element is And, and the output is connected to the input of the additional memory block, the output of which is connected to the third input of the second block of the output, while the outputs of the additional bit switch are connected to the second and third inputs of the additional block pgm tee, and the Additional key input is connected to the output of the first element I.

Description

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The invention relates to a pulse technique, and can be used, for example, in telegraphy to receive and record the duration of unipolar signals.

According to the main author. St. No. 951706 is known a two-level optoelectronic switch comprising two LEDs, three photodiodes, a transistor switch, a linear amplifier, an inverter, two delay elements, two sampling units, a single pulse shaper, two AND elements, a memory block, and a bit switch. The input of the transistor switch is connected to the power bus via the first photodiode optically coupled to the first LED, and to the common spike through the second photodiode optically coupled to the second LED. The output of the transistor switch through the inverter is connected to series-connected delay elements. The third photodiode is optically coupled to the first LED and connected between the power bus and the primary input of the first sampling unit, the second input of which is connected to the output of the first element I. connection delay elements. The output of the second delay element is connected to the first input of the second sampling unit, the second input of which is connected to the output of the memory block. The input of the memory unit is connected to the output of the first liter of the sampling unit. The outputs of the bit key are connected to other inputs of the memory unit. The input of the bit switch is connected to the output of the second element I, the second input of which is connected to the output of the transistor switch. The second input of the first element And is connected to the output of the inverter. The output of the second sampling unit is connected to the input of the linear amplifier, the output of which is connected to the cathode of the second LED, the anode of which is connected to the power bus. The output terminal is connected to the output of a transistor key, the input terminals are connected to the terminals of the first LED C1.

The known two-level optoelectronic switch allows to register unipolar signals with a variable amplitude of the current settings relative to two levels, each of which is located at the beginning of the edges of the received signal. In this case, the second registration level in the switch is set automatically, depending on the amplitude of the current signal of the recorded signal.

In the technique of transmitting a discrete IN formation, for example in telegraphy,

often there is a need to register; stratification of the duration of unipolar signals with variable amplitudes of not only current, but also current-free premises;

So, for example, in the case of transmission of unipolar telegraph signals over a communication channel, which is a long physical line with randomly varying parameter 1 "1 (such a channel can be an air telegraph line when exposed to atmospheric factors leading to a change in values the resistance of the duck and the distributed capacitance) it is possible that the amplitude of not only the current premises, but also the amplitudes of the current-free premises, is random in time.

In order to ensure high accuracy of registration of single-pole signals with variable amplitude of a current, in a known two-level optoelectronic switch it is necessary to manually set each time a new value of the first (lower) registration level determined by the quiescent current of the linear amplifier and for each amplitude of the current flow to place it at the beginning of the front signal buildup, which is a time consuming task during operation. If the amplitude of the currentless sending of the recorded signal changes, the case; 0, this results in a decrease in the accuracy of the recording of unipolar signals.

In addition, with an accidental increase in the amplitude of the current-free signaling of the recorded signal above the first registration level (located at the beginning of the rising front), the known two-level switch can stop normal operation, and registration of such signals will not occur, which reduces the reliability of operation.

Thus, the disadvantages of the known two-tier optoelectronic transponder keys are the difficulty of tuning during operation and the low reliability of operation when recording unipolar signals with randomly varying amplitude of the current-free signals.

The aim of the invention is to simplify the setup during operation and improve the reliability of the operation of a two-level optoelectronic switch.

The goal is achieved by the addition of a memory block, a bit switch, a sampling block, the first input of which is combined with the first input of the first block of the sample, the second input is connected to the output of the additional memory block, in the two-level optoelectronic switch. The output of which is connected to the third input of the second sampling unit, while the outputs of the additional bit switch are connected to the second and third inputs of the additional memory block, and the input of the additional bit is th switch is connected to the output of the first item I. In FIG. Figure 1 shows a diagram of a two-level optoelectronic switch; in fig. 2 - time diagrams that show his work. The two-level optoelectronic switch contains a transistor switch 1, the input of which is connected to the power supply bus 2 via the first photodiode 3, optically connected to the first diode 4, and to the common bus 5 through the second photodiode 6, optically coupled to the second light code 7 Inverto 8, whose input is connected to the output of key 1, and the output to the input of the first delay element 9, the third photodio 10, optically coupled to the LED 4 and connected in the opposite direction between bus 2 and the first input of the first sampling unit 11, the second input is connected to the output m of the first element H 12, the first inputs of the element I 12I of the second element 1 are combined and connected to the output of a single pulse generator 14, the input of which is connected to the output of delay element 9 and the input of second delay element 15, whose output is connected to the first input of the second block 16 the samples, the second input of which is connected to the output of the 17th unit, the outputs of the bit switch 18 are connected to the corresponding inputs of the memory block 17, and its input to the output of the And 13 element, the output of the 16th sampling unit is connected to the input of the linear amplification 19, the output of which yuchen k; the LED of the LED 7, whose anode / is connected to the power bus 2, an additional sampling unit 20, the first input of which is combined with the first input of the sampling unit 11, the second input is connected to the output of the And 13 element, and the output is connected to the input of the additional memory block 21, the output of which is connected to the third input of the sampling unit 16, the outputs of the additional bit switch 22 are connected to the corresponding second and third inputs of the memory unit 21, and its input to the output of the And 12 element. The output of the transistor switch 1 is switch output 23. The input terminals 24 and 25 are connected to the terminals of the first LED 4. In FIG. 2 marked: Q - input current through terminals 24 and 25; c5 is the input voltage of shaper 14; g is the output voltage of shaper 14; i, is the output voltage of sampling unit 11; E - output voltage of the block 20. sample; - output voltage of memory block 17 output voltage of memory block 21; - the output voltage of the second element 15 delay; and - the output current of the linear amplifier 19; VC is the output voltage of the device. Two-level optoelectronic switch operates as follows. If there is a single-sided signal at the input 24 and 25 and when the amplitude of the current-free package is equal to zero, the current through the LED 4 and, accordingly, through the photodiodes 3 and 10 does not leak. The transistor switch 1 is closed, and a low voltage level is removed from the output of the inverter 8, which through successively connected delay elements 9 and 15 is fed to the first (control) input of the sampling unit 16. If there is a low voltage level at the control input 16, the block 16 provides signals to its output to its third input (i.e., it switches the third input and output), so at that time the input of the linear amplifier 19 A signal is output from the memory block 21. If the amplitude of the currentless parcel is equal to zero, the voltage at the output of the memory unit 21 and, accordingly, at the input of the linear amplifier 19 is absent, therefore the linear amplifier 19 is in the quiescent mode. The quiescent current of the linear amplifier 19 flows through the LED 7, therefore the photodiode 6, optically coupled to the LED 7, is in the valve mode and provides a negative mixture between the base and the emitter of the transistor switch 1 and sets the lower level of signal detection when the amplitude is zero. parcels (the operating point of the linear amplifier 19 is chosen so that, in quiescent mode, a current flows in its collector circuit and in the LED circuit 7, which determines the lower level of operation of key 1 when the amplitude of the parcel current is equal to zero). time elements And 12 and 13 are turned off and blocks 11 and 20 of the sample are closed. When current is received at the input terminals 24 and 25 of sending a same-field signal (FIG. 2a through LED 4, respectively, and a current flows through photodiodes 3 and 10.) When current through LED 4 reaches the value corresponding to the turn-on threshold of transistor switch 1, the limit current in this case

When the linear amplifier 19 is at rest, the key 1 is turned on and the output of the port 23 appears Ariana Surge.

After the delay time itg, determined by the delay element 9, a positive voltage drop is received at the input of the driver 14 (FIG. 25), as a result of which a single pulse of FIG. 2b) appears at the output of the driver 14, which is fed to the first inputs of the elements E12 and 13 . At this time, high levels of voltage are present at the inputs of the And 12 element, as a result of which a high level of voltage is generated at its output, which for a short time turns on the sampling unit 11 and the additional bit switch 22. The signal from the first run of the sampling unit 11 ( Fig. 2d) enters memory block 17, while at the output of sampling unit 20 there remains a low potential (Fig. 2E) f, and the output of memory block 17 stores the pulse amplitude from sampling unit 11 (Fig. 2e). Element And 13 remains off (a short-on switching bit 22 could reset the analog information in memory block 21 (FIG. 2g, which there would be if the amplitude of the currentless package were not zero). :

The delay element 9 and the single pulse shaper 14 provide a sample for storing the amplitude of the current parcel at the point in time when the amplitude of the current parcel is already established. The sampling is carried out on a time interval that is least affected by interference (It is most expedient to carry out sampling in the middle part of the elementary parcel, for a time much shorter than the duration of the elementary parcel). After completion of the sampling, the output voltage of the memory block 17 (phi1.2e) is set to the amplitude of the voltage, proportional to the amplitude of the current parcel, and is fed to the second input of the sampling block 16. To the input of the linear amplifier 19, the voltage from the output of the memory block 17 is supplied only when the first (control) input of the sampling unit 16 has a high voltage level, i.e. through the time tr / g, determined by the delay element 15 (FIG. 2z (the element behind: the support 15 in this case eliminates the false triggering of the switch in the time interval between the end of the sample of the current parcel amplitude and the beginning of the falling edge of the short-term crushing).

The total delay time of the elements 9 and 15 of the delay should not exceed the duration of the recorded elementary current package.

After arriving: 1i voltage from the output of the block 17 p 1 mi / fig. 2e, / to the input of the amplifier 19, the current of the collector circuit of the amplifier increases (Fig.2i, and accordingly, the current increases through the LED 7, as a result of which the second registration level is set in the switch, the value of which is proportional to the amplitude of the input signal current and is always less than the amplitude is by a predetermined value. In this case, the state of the switch does not change, i.e. the voltage level at the output 23 remains low (Fig. 2icJ.

By selecting the operating point of the linear amplifier 19, it is possible to ensure, at any current-signal amplitude, the position of the second registration level at the very beginning of the decay front.

Decreasing the amplitude of the current parcel (the beginning of the currentless parcel, Fig. 2oi) reduces the current through the LED 4 and the photodiodes 3 and 10.

When the current through the LED 4 reaches the value corresponding to the switch-off threshold of key 1, detected by the current through LED 7 and proportional to the current amplitude, switch 1 is turned off and a high voltage level appears at output 23 (Fig. 2). a delay element 9, a negative voltage drop arrives at the input of the former 14 (Fig. 2S}, as a result of which, on the former, the former 14 again appears a single pulse of Fig. 2. Now the And 13 for a short time turns on, temporarily turning on sampling block 20 (Fig. 2e) and a bit switch 18. Element I 12 remains off at this time.

The signal from the first input of the sampling unit 20 enters the memory unit 21 (Fig. 2), where its amplitude is memorized. The delay element 9 and the single pulse former 14 using block 20 provide a sample for storing the amplitude of the currentless parcel at the moment when the amplitude of the currentless parcel has already been established. The sampling is again carried out in the time interval that is least affected by interference (as well as, the sampling is carried out in the middle part of the elementary parcel (currentless), for a time much shorter than the duration of the elementary parcel). The briefly turned on bit 18 clears the analog information in memory block 1-7. In order to avoid unstable operation of the switch, the bit 18 must not completely reset the analog information in the block

17, but only part fE (FIG. 2e). Since at the time of resetting the information in block 17, the well block 17 remains for some time connected via block 16 to the input of the linear amplifier 19, it is necessary that the switch of the switch of the linear amplifier 1, reduced as a result of the breakdown of the current, did not lead to a decrease in the level of switch registration below the maximum allowable amplitude of the current-free parcel. The adjustment of the amount of information reset in the memory block 17 using the bit switch 18 can be performed, for example, by changing the internal resistance of the bit switch 18.

After completing the sampling amplitude of the currentless parcel at the output of the memory block 21 of FIG. 2t) sets the voltage amplitude, is proportional to the amplitude of the current-free parcel, and arrives at the third input of the sampling unit 16. However, at this point in time, the first (control) input of the block 16 still has a high voltage level and prevents the voltage from the output of the memory block 21 to the input of the linear amplifier 19 (the current from the linear amplifier 19 continues to flow to the input of the linear amplifier 19) block output 17 pa. m tee).

The input of the linear amplifier 19 from the output of the memory unit 21 begins to flow when the first (control) input of the sampling unit 16 has a low voltage level, i.e. over time.determinable delay 15 delay element 15 delay in case it eliminates false triggering of the switch in the time interval between the end of the sampling amplitude of the currentless burst and the beginning of the rising edge of the signal from short-term impulse noise.

The total delay time of the elements 9 and 15 of the delay in this case should not exceed the duration of the registered elementary current-free parcel.

After the voltage from the memory unit 21 arrives at the input of the linear amplifier 19, the current of the amplifier's collector circuit decreases (Fig. 2i) and, accordingly, the current decreases through the LED 7, as a result of which the first register level is set, the value of which is proportional to amplitude currentless parcel of the input signal and is always greater than this amplitude by a specified amount. In this case, the state of the switch does not change (at output 23, a high level of voltage (Fig. 2K), since at this time the amplitude of the input signal (currentless parcel) is less than the newly established level of recording.

five

By selecting the operating point of the linear amplifier 19, it is possible to ensure, at any amplitudes of currentless parcels, the position of the first registration level at the very beginning of the rising front.

When the switch arrives at the input of the current parcel again and when its amplitude reaches the first one (the lower registration level located at the very beginning of the front

5 ramp up, at the switch output 23, a low level of Tprech appears again. Subsequently, processes similar to those described occur in the switch.

0

Thus, in the proposed two-level optoelectronic switch, unlike the prototype, each of the registration levels are automatically set depending on the amplitudes of the respective premises (current and current) and are located at the beginning of the corresponding edges of the received signal (rising edge and falling front).

0

The use of a two-level optoelectronic switch as an input device in receivers of electronic telegraph devices, working in conjunction with automatic telegraph stations, in transitional telegraph devices will ensure high accuracy of recording the duration of signals transmitted over communication channels with variable parameters and simplify setup during operation. and improve the reliability of telegraph receivers operating on dial-up lines, as well as on the lines of communication with the leak,

5 f.e. On long physical lines.

Claims (1)

TWO-LEVELS! ® OPTOELECTRONIC SWITCH according to ed. St. "951706, characterized in that, in order to simplify the configuration during operation and increase the reliability of the switch, it additionally includes a memory unit, a bit key, a sampling unit, the first * input of which is combined with the first input of the first sampling unit, the second input is connected to the output the second element And, and the output is connected to the input of the additional memory block, the output of which is connected to the third input of the second sample block, while the outputs of the additional bit key are connected to the second and third inputs of the additional block memory, and the input of the additional key is connected to the output of the first element I.