SU1518902A1 - Demodulator of phase-manipulated signals - Google Patents

Abstract

The invention relates to communication technology. The purpose of the invention is to improve noise immunity. The demodulator contains a frequency multiplier 1, narrowband filter 2, frequency dividers 3 and 5, phase shifter 4, delay lines 6 and 8, phase detector 7, ADC 9, driver 10 pulses, binary code accumulator unit 11, delay element 12, decoder 13, a controlled phase shifter 14 and a detector 15. The goal is achieved by providing an adjustment of the phase of the reference oscillation by the magnitude of the phase jump. As a result, despite the rapid fluctuations of the phase of the reference voltage, uniformly distributed over the interval 0-2ϕ, the phase of the voltage at the second input of the detector 15 remains constant. 2 Il.

Description

ate

The invention relates to communication technology and can be used in data transmission systems of a signal with phase shift keying.

The purpose of the invention is to increase noise immunity.

Fig. 1 shows the structural electrical circuit of the demodulator of the phase-shifted signals; figure 2 - block diagram of the adder-drive.

The demodulator of phase-shifted signals contains a frequency multiplier 1, narrowband filter 2, frequency divider 3, phase shifter 4, additional frequency divider 5, delay line 6, phase detector 7, additional delay line 8, analog-to-digital converter (1B) 9, shaper 10 pulses , block I1 of the accumulator of the binary code accumulator, delay element 12, decoder 13, controllable phase shifter 14, | detector 15.

The accumulator adder unit 11 includes a t-bit accumulating adder 16 according to a module, logic gates 17, a delay element 18, RS-flip-flops 19 and an inverter 20.

The demodulator of the phase-shift keyed signals operates as follows.

The phase-manipulated signal is fed to the input of multiplier 3, where during the frequency doubling process, the phase shift of the signal is eliminated, and in narrowband fichgre 2 the influence of interference is reduced. Using the divider 3 and the phase shifter A, a reference voltage of the required frequency and phase is obtained, which is fed to the input of the additional divider 5 directly and through the additional delay line 8 to the input of the controlled phase shifter 14.

Prior to the appearance of the phase jump of the reference voltage, the difference in the voltage phases at the inputs of the detector 7 is constant and is determined by the delay time of the line 6. When the phase jump appears at the output of the divider 5, its magnitude D Lfj is reduced by a factor of two.

Such a change in the scale of the phase plane of the reference voltage allows measuring and identifying in the interval 0–20, at the output of the phase detector 7, an error voltage proportional to Dsrr which, with a sinusoidal operating characteristic of the detector 7, equals

V v

(t) -Vo (t.t)

sin, G

0

SRV OH - it is -3 2 Obviously, when it is applied (., V. The abrupt voltage at the output of the phase detector 7 is fed to the driver 10, which at the output generates a pulse allowing the conversion of the output voltage of the detector 7 to a binary code. This operation em ADC, number of outputs

whom

P

 depends on requirements5

0

five

0

five

0

five

0

five

my phase correction accuracy.

The binary binary code with ADC 9 goes to block 11. In addition, from the additional output of ADC 9, an additional input of block 11 receives an information signal on the sign of the output voltage of the detector 7. Moreover, if the magnitude of the phase jump lies within 0-T, then the voltage is positive, and if G-2 p is negative.

ADC 9 and block I1 allow the inverse scaling of the phase plane.

The operation of accumulator adder 16 is constructed on the basis of a truth table, in which at the intersection of the i-ii value of the row and the value of the j-column, the result of the sum is written, which can be represented by the relation

W; oi; / 3j (mod n), (1) where, fi- are terms, and is the result of a sum.

The truth table for p 16 looks as follows (table)

For example, for oi 9, / 3j 12, then about ;; 21, and the sum modulo n 9 + 12 mod 16 5, which is equal to the remainder of dividing the sum L; + - on the number of

The described algorithm of operation is implemented in the adder method, since the terms are represented in binary code.

The basis of the node that performs the summation operation is the usual binary adder, equipped with additional logical circuits that provide the execution of the addition operation over the corresponding module.

But since the addition is complete in binary code and m is the number of bits of the adder is equal to the whole logarithm of n on the base two

m login

TO binary accumulative cywtaTOp 16 (with n 2) can be implemented by connecting m - the number of binary bits of the adder without additional logic circuits and feedback.

In addition to accumulating adder 16, block 11 constructively includes a line of m - the number of RS-flip-flops 19, forming the second memory level, delay element 18 and m logic circuitry And 17, which allow timely rewriting of the generated code from accumulating adder 16 to the second level the memory of the RS-flip-flops using the control signal received after the end of the transient processes in the accumulating adder 16 and resetting the RS-flip-flops 19.

The binary code is fed to the corresponding inputs of the decoder 13. The output signal from the decoder 13 is fed to one of the control input phase shifter 14, which provides for the correction of the phase of the reference oscillation by the magnitude of the phase jump.

If the next spontaneous phase jump of the reference voltage occurs over time, the demodulator determines the magnitude of this jump, the corresponding binary code is added to the primary jump code stored in block 11 and overwritten to the second memory level of block 11. Next The new phase jump is adjusted as the first. At subsequent phase jumps, the sum of their values may exceed 27.

In this case, the accumulating adder in block 11 allows to take into account the frequency of trigonometric functions describing the reference signal.

The operation of the demodulator of the phase-shift keyed signals can be seen in a specific example.

Let the interval 0-211 be divided into 16 subintervals () by 22.5.

Each angle value corresponds to a 4-bit binary code (see Table 2).

In general, n must be an integer power of 2 (8 through 45); (16 to 22.5 °); (32 to 11.25 °); (64

on 5,6), etc.

When n 16 ADC 9 should have eight points of reference and the number of outputs k-.l 3.

The fourth (kth) bit, the oldest for block 1I, is generated using an inverter 5 based on the signal from the additional output of the A / D converter 9, depending on the polarity of the converted Q in the binary voltage code. With a positive polarity, this is 1, with a negative O.

Then a phase jump at the output of the 4Atfc f 315 phase shifter (-45 °) at the output of the 5 DCHe -22.5 divider 5 will lead to the appearance of the phase detector 7 at the output of the UFD / sin LM converter Aid 9 to the code - 010.

However, the same code would be formed at the output of the AShch and in the case of a LS / St 5 phase jump. This ambiguity allows us to resolve the signal 6 of the additional output of the ADC, carrying information about the sign of the output voltage of the phase detector 7. Therefore, in the case under consideration, the phase jump uQ crf, -43- is the corresponding code 1010, and uq; c. 0010.

At the output of block 11, a 0 code 1010 is generated, and a signal is output at the corresponding output of the decoder 13, which will determine the amount of the corrective phase shift in the controlled phase shifter 14 (-45 °).

Thus, despite the rapid fluctuations of the phase of the reference voltage, evenly distributed over the interval 0-21, the voltage phase at the second input of the detector 15 remains

Q STANDING.

five

Formula inventions

A demodulator of phase-shift keying signals containing a detector and therefore 5 connected frequency multiplier, narrowband filter, frequency divider and phase shifter, serially connected delay line and phase, detector, second input

0 which is connected to the input of the delay line, the combined first input of the detector and the input of the frequency multiplier are the input of the demodulator, and the output of the detector is the output of the demodulator 5, characterized by the fact that an additional delay line has been introduced into it, frequency divider, analog 7151

digital converter (/ Ш) and serially connected pulse shaper, delay element, accumulator adder unit, decoder and control phase shifter, the output of which is connected to the second detector input, and input through an additional delay line to the combined output of the phase shifter and the additional frequency splitter input .

9028

the output of which is connected to the combined inputs of the delay line and the phase chip, the output of which is connected to the combined signal inputs of the ADC and pulse shaper, the output of which is connected via the ADC to the information inputs of the accumulator accumulator, the additional input of the ADC is connected to the signal input.

ten

Note: O, 1, 2, ..., 15 - possible values of the terms and the results of the sum.

Table 1

table 2

FIG. 2

Claims (1)

Claim A phase-shift signal demodulator comprising a detector and a series-connected frequency multiplier, a narrow-band filter, a frequency divider and a phase shifter, after a specific example. Let the interval 0-257 be divided into 16 sub-intervals (n = 16) at 22.5 °. Each angle value corresponds to a 4-bit binary code (see Table 2). In the general case, η must equal the integer power of 2 (8 by 45); (16 to 22.5 °); (32 to 11, 25 °); (64 to 5.6 °), etc. well-connected delay line and phase detector, the second input 50 of which is connected to the input of the delay line, the combined first input of the detector and the input of the frequency multiplier are the input of the demodulator, and the detector output is the output of the demo55 of the modulator, characterized in that, in order to increase the noise immunity, into it introduced an additional delay line, an additional frequency divider, analogue7 digital converter (MP) and serially connected pulse shaper, delay element, accumulator-accumulator block, des fractor and control phase shifter, the output of which is connected to the second input of the detector, and the input through an additional delay line - to the combined output of the phase shifter and the input of an additional frequency divider, the output of which is connected to the combined inputs of the delay line and the phase detector, the output of which is connected to the combined signal inputs of the ADC and a pulse shaper, the output of which through the ADC is connected to the information inputs of the adder-drive unit, to the signal input of which an additional ADC output is connected. Table I + 0 I 2 3 4 5 6 7 8 9 10 eleven 12 thirteen 14 fifteen 0 0 1 2 3 4 5 6 7 8 9 10 eleven 12 thirteen 14 fifteen 1 1 2 3 4 5 6 7 8 9 10 eleven 12 thirteen 14 fifteen 0 2 2 3 4 5 6 7 8 9 10 eleven 12 thirteen 14 fifteen 0 1 3 3 4 5 6 7 8 9 10 eleven 12 thirteen 14 fifteen 0 1 2 4 4 5 6 7 8 9 10 eleven 12 thirteen 14 fifteen 0 1 2 3 5 5 6 7 8 9 10 eleven 12 thirteen 14 fifteen 0 1 2 3 4 6 6 7 8 9 10 eleven 12 thirteen 14 fifteen 0 1 2 3 4 5 7 7 8 9 10 eleven 12 thirteen 14 fifteen 0 1 2 3 4 5 6 8 8 9 10 eleven 12 thirteen 14 fifteen 0 1 2 3 4 5 6 7 9 9 10 eleven 12 thirteen 14 fifteen 0 1 2 3 4 5 6 7 8 10 10 eleven 12 thirteen 14 fifteen 0 1 2 3 4 5 6 7 8 9 eleven eleven 12 thirteen 14 fifteen 0 1 2 3 4 5 6 7 8 9 10 12 12 thirteen 14 fifteen 0 1 2 3 4 5 6 7 8 9 10 eleven thirteen thirteen 14 fifteen 0 1 2 3 4 .5 6 7 8 9 10 eleven 12 14 14 fifteen 0 1 2 3 4 5 6 7 8 9 10 eleven 12 thirteen fifteen fifteen 0 1 2 3 4 5 6 7 8 9 10 1 ) 12 thirteen 14 Note: 0, 1, 2, 15 - the possible values of the terms and the results of the sum. Lower Binary code D.5 At the exit 0 0000 0 22.5 0001 AND 2 45 0010 22.5 67.5 001 1 33.7 90 0100 45 112.5 0101 56.2 135 01 10 67.5 157.5 01 1 1 78.7 180 1000 90 202.5 1001 -11.2 225 1010 -22.5 247.5 101 1 -33.7 270 1,100 -4? 2925 1101 -56.9 315 11 10 -67.5 337.5 1111 -78.7 Binary code at the output of the ADC 9 table 2 K ~ th output of the ADC 9 Binary code at block 11 output 000 + 0000 001 + 0001 010 + 0010 01 1  + 001 1 10Q + 0100 101 + 0101 1 10 + 0110 111 + 01 1 1 000 - 1000 001 - 1001 010 - 1010 011 - 101 1 but - 1100 101 - 1101 110 - 1110 110 1111