SU1700564A1 - Microprogramming control processor - Google Patents

Abstract

The invention relates to digital computing, in particular to high-performance microprogrammed processors in computers and computer systems. The aim of the invention is to increase productivity by reducing the time when switching from process to process in a multiprogram operation mode. The goal is achieved by the fact that the processor with firmware control contains a block 1

Description

The invention relates to computing and can be used to create specialized and versatile high-performance computers and systems.

The aim of the invention is to increase productivity by reducing the time when switching from process to process in a multiprogram operation mode.

This goal is achieved due to the fact that the organization of a multiprogram mode of operation excludes temporary losses associated with the interpretation of commands of the internal language. Switching from process to process is accomplished in one microinstruction. In addition, this device allows you to avoid unnecessary time spent on managing the queue of processes that are waiting for setting up in the shared memory by providing each process with the opportunity to work with its own area of super-operative memory that stores the data it processes (the process context).

FIG. 1 shows a block diagram of a processor with firmware control; in fig. 2 - the structure of the scoring scheme; in fig. 3 is a block diagram of the formation of a firmware address; in fig. 4shema arithmetic logic unit; in fig. 5 is a block circuit diagram; in fig.

6- time diagrams of the processor.

The processor with the firmware control contains the block 1 of the formation of the microprogram address, the register 2 of the microprogram address, the block 3 of the memory of microcommands, the register 4 of microinstructions, the decoder 5 of the control microinstructions, the arithmetic logic unit 6. register

7 addresses, memory block 8, synchronization block 9, register memory blocks 10, page memory block 11, process address memory block 12 pages register, 13 pages,

the decoder 14 page number, scaling circuit 15, the trigger 16 mode, the first switch 17, the second switch 18, the third switch 19, the first bus driver 20, the second bus driver 21, the third bus driver 22, the fourth bus driver 23, the first element And 24, the second element is AND 25, the third element is AND 26, the fourth element is AND 27, the fifth element is AND 28, the first element is OR 29, the second element is OR 30, the third element is OR 31, the fourth element is OR 32, the data bus 33, the address bus 34, input 35 of the initial setup, output 36 of the address of the scaling circuit, output 37 The number of processes, the counting input 38 of the scaling circuit, the input 39 of the address of the scaling circuit, the input 40 of the recording of the number of processes of the scaling circuit, the information input 41 of the scaling circuit, the input 42 of the initial setting of the scaling circuit.

In addition, in FIG. 2 shows an address counter 43, a comparison circuit 44, a process number register 45, a fifth element OR 46.

The block of the formation of the firmware address (Fig. 3) shows: control function decoder 47, fourth switch 48, fifth switch 49, flag trigger 50, sixth element 51, seventh element 52, first input 53, second input 54, third input 55, fourth input 55, fifth input 57, first output 58, second output 59.

FIG. 4, an operation code decoder 60, an arithmetic logic circuit 61, a result register 62, a sixth switch 63, a seventh switch 64, a fourth bus driver 65 are indicated.

Block 6 contains an operation code input 66, a synchronization input 67, a transfer input 68, a transfer output 69, information input / output 70, address output 71, write control output 72, register information input / output 73, sync output 74, register address output 75, entry 76 reading

FIG. 5 denotes a clock generator 77, a frequency dividing trigger 78, an eighth element E 79, a first 80, a second 81 and a third 82 outputs of block 9.

FIG. 6 shows diagrams: A - on the first output of the synchronization unit 9, B - on the second output of the synchronization unit 9, C

- on the third output of the synchronization unit 9, H. on the output of register 2 of the microprogram address, D - on the output of block 3 of the microprogram memory, E - on the output of the register 4 micro-instructions, G - on the output of the signal. Switching the process of the decoder 5 control micro-instructions, M

- at the output of the block 12 of the memory of the addresses of processes, K - at the output of the block of the 11 pages memory, L - at the output of the first switch 17, M - at the output of the register 13 pages.

A firmware processor (Fig. 1) contains a firmware address generation unit 1, which is designed to generate the address of the next microcommand under a control action from the microcommand. The control function decoder 47 included in block 1 (Fig. 3) is intended to generate control signals defined by the control field of the microcommand address. The address control field is fed to the input of the decoder 47 via the second input 54 of block 1. The fourth switch 48 is designed to form the next microcommand address by the address control field, taking into account the output transfer of the arithmetic logic unit 6, which arrives at the fourth input 56 of block 1 and the current microcommand address, coming through the first input 53 of the block 1.

The fifth switch 49 is designed to generate the transfer input signal for the arithmetic logic unit 6 outputted to the first output 58 of block 1, the flag trigger 50 to store the transfer signal of the arithmetic logic unit 6, the sixth And 51 element to form the address of the next microcommand from information located on the data bus 33 and coming through the fifth input 57 of block 1. The seventh element 52 is intended to form the address of the next microcommand from the address of the previous microcommand that comes in through the third input 55 of block 1 formation of the firmware address. The outputs of the switch 48, elements And 52 and 51 have three states, the address of the following microcommand is given to the second output 59 of unit 1.

Register 2 of the firmware address is designed to store the current firmware address for one microcommand cycle. Its output is connected to the first input of the microprogram address formation unit 1 and to the address input of the microcommand memory block 3, which ensures the output of the corresponding microcommand to its output.

Register 4 of the micro-instructions is designed to memorize the current micro-instructions for one cycle. The microcommand of the processor contains four fields: the address control field, which arrives at the second input of the microprogramming address generation unit 1; the field of control microinstructions, which is fed to the input of the decoder 5 of the control- 5 leveraging microinstructions and to the third input of unit 1; the reading field, which enters the input of the blocks, the outputs of which are connected to the data bus 33, and the operation code field, which arrives at the corresponding input of the arithmetic unit of the logical block 6.

The decoder 5 control microinstructions is designed to generate control signals from the field of control microinstructions microcommands. The outputs 5 of the decoder 5 are connected to the corresponding controllable elements of the processor.

The arithmetic logic unit 6 is intended for arithmetic logic processing of information received at its two inputs / outputs (information and register information) in accordance with the operation code at its input of the operation code. The result, depending on the operation code, is on the information input-output, input-output register information and output of the block 6 address. In accordance with the structure of block 6 (FIG. 4), the operation code decoder 60 is intended to form from a sync signal and the code field control command microcommand operations for the arithmetic logic circuit 61, switches 63 and 64, result register 62 and output control 5 signals at sync output 74 for blocks 10 of the register memory and control of record 75 for the address register 7. The clock signal is fed to the input of the decoder 60 through the synchronization 67, and the operation code through

0 the same input 66 of the arithmetic logic unit 6.

Arithmetic logic circuit 61 is designed to perform arithmetic logic operations on operands,

5 coming to its inputs from the outputs of the switches 63 and 64, taking into account the transfer coming through the input 68. The result of the operation goes to the output 71 of the address and the input-output 73 of the register information and to the input of the register 62 of the result. Register 62 results

is intended for storing the results of operations performed by arithmetic logic 61, writing to register 62 occurs on a signal from the output of decoder 60. Sixth 63 and seventh 64 switches are used to supply operands to the inputs of arithmetic logic 61, Operands can be received either through information input-output 70, or through the input-output 73 of the register information. The switches 63 and 64 are controlled by signals from the outputs of the decoder 60 of the operation code. Fifth bus driver 65 is designed to output the contents of the result register 62 to the information output 70 of the arithmetic logic unit 6, the output of the bus driver 65 has three states neither

The address register 7 stores the new memory address obtained at the address output of block 6 as a result of the current operation, if there is a write control signal at the same output of block 6, the information output of the register 7 is connected to the address bus 34, the new memory address arrives at address bus 34 all the time until the next recording of information into register 7. RAM memory unit 8 is designed to store intermediate results of the operations of the microprocessor processor. The unit 8 records the information appearing on the data bus 33 by the data recording signal received from the output of the decoder 5 of the control microinstructions of the same name. Unit 8 provides information to the data bus 33 via the read signal coming from the read output of register 4 microcommands. The address of the address to block 8 corresponds to the information on the address bus 34. The output of block 8 has three states.

The synchronization unit 9 is designed to form the control clock signals of the processor, the sync pulse generator 77 — to form at its output a sync sequence of square pulses with a duty cycle of two, which goes to the counting input of the trigger 78 and the first input of the eighth element I 79 (FIG. 5). The second input of this element receives the signal of the inverse output of the trigger 78. As a result, the output of the eighth element I 79 generates clock signals with a duty cycle of four, which correspond to the first output 80 of the synchronization unit 9 (diagram A of FIG. 6) The forward output of the trigger 78 generates a signal corresponding to the second exit

81 of block 9 (diagram B of FIG. 6), a signal corresponding to the third output is set at the inverse output of the trigger 78

82 of block 9 (diagram B of FIG. 6).

Main and additional units 10

the register memory is a non-operative memory and is organized in the form of pages. Each page is intended for storing in a super-operational way information specific to one of the processes - the context (image) of this process. Page cells are designed to store the results of intermediate arithmetic logic operations.

5 block 6.

Each page of block 10 of the register memory is designed to work with one of the existing processes in the processor. The page number corresponds to the name of the process. Depending on what process is currently being serviced, the control input of the corresponding page receives a signal from the output of the decoder of 14 pages. Information is recorded into the page selected in this way by a signal from the sync output of the arithmetic logic unit 6 to the page sync input. Information for recording and readable information appear on the information input-output of the page connected to the input-output of the register information of the arithmetic logic unit 6. The register address that is accessed in the page is determined by the information on the output of the register address of the arithmetic logical block 6.

The page memory unit 11 and the process address memory unit 12 are designed to store information about existing

In order to process them in order of priority, the access address is always set the same for both units. In the absence of recording entries of blocks 11 and 12 of the memory of the corresponding signals, information from blocks 11 and 12 is read at the address set at their address inputs. The number of cells of blocks 11 and 12, the cell width of block 11 are determined by the maximum allowable number of existing processes. The cell width of the memory unit 12 is determined by the address width of the micro-instructions.

The page memory unit 11 is used to store the page numbers of the histological memory unit 10, designed to work with existing processes in the processor. The page number is the process name. Information from the data bus 33 is used to write to the memory 11. The write address is determined by the information at the output of the first switch 17 and coincides with the write address of the process address memory 12. Process address memory block 12 provides storage of process start addresses. In contrast to block 11, information for writing to memory block 12 is received through the second switch 18 either from the data bus 33 or from the output of block 3 of microcommand memories. The latter is necessary to ensure that the process returns to the address in which it was taken out of service during subsequent maintenance of this process. The recording in blocks 11 and 12 is always separate, except for the recording by the initial installation, the reading is carried out in the absence of a recording.

The register of 13 pages is intended to store the page number of the block 10 of the register memory of the process that is currently being serviced by the processor. The information input of the register 13 receives information from the output of the page memory block 11, and it is written to the register 13 upon arrival of the signal to the synchronous input of the register 13 when the new process is serviced.

The decoder 14 of the page number is designed to decrypt the process name in order to put the required page of the register memory 10 into operation with the process. The signal generated at the corresponding output of the decoder 14 is fed to the control output of one of the pages of the block 10 register.

Scaling circuit 15 is designed to store the address of the process being maintained and to store the number of existing processes. The number of processes in the processor is stored in the number of processes register 45 included in the scaling circuit 15 (FIG. 2), and is recorded in the register 45 from the data bus 33 connected to the information input 41 of the scaling circuit 15, according to the write signal the number of processes arriving at the input 40 of the scaling circuit 15 from the output of the decoder 5 control microinstructions. The number of processes can be read through the output 37 of the scaling circuit 15 of the same name. The address of the process currently being serviced is contained in the counter 43 of the address where it is either written from the data bus 33 connected to the information output 41, or incremented by one to the contents of the counter 43, An increase in the address per unit occurs according to the process switching signal from the decoder 5 output of the same name controlling

microinstructions simultaneously with the synchronization signal from the third output of block 9 to the counting input of counter 43 via input 38 of scaling circuit 15. If the number of processes in register 45 compares with the contents of counter 43, comparison circuit 46 will generate a signal that sets counter 43 to zero, which corresponds to the maintenance of the zero process.

0 The mode trigger 16 is designed to provide access to information about the processes stored in blocks 11 and 12. The mode trigger 16 is controlled by software using the control microinstructions field. In one state, the trigger 16 connects through the first switch 17 the address bus 34 to the address outputs of the blocks 11 and 12, and through the second switch 18 to the data bus 33

0 input data block 12 memory addresses of processes.

The first switch 17 is designed to connect to the address inputs of blocks 11 and 12 of information from the address bus 34 or

5 address output 36 of the scaling circuit 15, depending on the signal at the output of the trigger 16 mode.

The second switch 18 is designed to connect to the data input information from the data bus 33 or the outputs of the microcommand memory block 3, corresponding to the microcommand address control field, depending on the signal at the output of the mode trigger 16.

5 The third switch 19 is intended to be connected to the information input of register 2 of the firmware address information from the output of the process address memory block 12 or from the second output of block 1

0 formation of the firmware address depending on the signal at the control input of the switch 19. To the control input of the switch 19, the signal comes from the output of the fourth element OR 32.

5 The first 20 and second 21 bus drivers are designed to issue data 33 to the bus 33, respectively, about the name and start address of the process being served from the outputs of blocks 11 and 12. The bus drivers are controlled by a microcommand reading field; the outputs of bus drivers 20 and 21 have three states neither

The third 22 and fourth 23 bus forwarders are intended for issuing to the bus 33 data the addresses of the process being serviced, respectively, from output 36 of the scoring circuit 15 and the number of existing processes from output 37 of the scaling circuit 15. Control or

the formers are carried out by the microcommand reading field; the outputs of the bus formers 22 and 23 have three states.

The first 24 and second 25 And elements are respectively used to form the recording signals for blocks 11 and 12 from the sync signal from the second output of the synchronization unit 9 depending on the signals at their first inputs, the third And 26 element to form a signal arriving at the counting input 38 of the recalculated circuits 15, from the sync signal from the third output of the synchronization unit 9 from the process switching signal from the same output of the decoder 5 control microinstructions.

The fourth element And 27 is designed to form a signal supplied to the synchronous input of the register 13 of the page, from the signal from the first output of the synchronization unit 9 depending on the signal at the first input of the element 27, the fifth element And 28 - to form the signal input to the number 39 record the processes of the scaling circuit 15, from the signal from the third output of the synchronization unit 9 and the signal recording the address of the scaling circuit from the equal output of the decoder 5 control microinstructions.

The first element OR 29 is designed to form a signal for supplying the second element AND 25 to the first input, meaning that information should be recorded in the process address memory block 12, the second element OR 30 - to form a signal for supplying the first element AND 24 to the first input that means that information should be recorded in block 11 of the page memory.

The third element OR 31 is designed to form a signal for supplying the third element AND 27 to the first input, meaning that information must be recorded in the 13-page register, the fourth element OR 32 is to form a signal for supplying the fourth switch 19 to the control input.

The processor works as follows.

At least one process is always in service in the processor. The processes have names that match the page addresses of the register memory block 10 and are stored in the page memory block 11. Each process is supplied with information about itself in the form of its name (the page number of the register memory block 10) and the initial firmware address. Processes are organized in a cyclic queue. The order in the queue is determined by the order of

following the addresses of the cells of blocks 11 and 12, in which information about the processes is recorded. The order of servicing the processes is t (consequently, at the addresses of the cells of the blocks 1% and 12,

storing information about processes. The cyclicality of the service process is provided by placing the process with a zero address after the service is removed from the process with the most senior address.

When setting up a maintenance process, it should be provided with access to the nominal page of block 10 of the register memory and be supplied with its initial micro5 program address as the address of the first microcommand. The address of the cells of blocks 11 and 12, which contain information about the process being maintained, and the number of processes existing in the processor,

0 is stored in the scaling circuit 15. The maximum allowable number of processes in the processor is determined by the width of the memory cell of the page memory block 11 and the corresponding register size of 13 pages. The process required for being in the processor is zero, which ensures the maintenance of the remaining processes and is generated by the initial installation signal in the firmware program. In addition, the processor provides for the following operations with processes: generation of new processes (within the limits of the maximum allowable number), reading

5 information about any process and scoring scheme 15, setting the process for maintenance, destruction of the process by pushing.

The generation of a zero process in the microprocessor processor occurs by applying to the processor an initial setup signal through input 35. This signal goes through the fourth element AND 32 to the control input of the third switch 19,

5 through the third element OR 31 to the first input of the element AND 27, through the second element OR 30 to the first input of the first element AND 24, through the first element OR 29 to the first input of the element AND 25, to the input of the initial setting of the register 7 address, to the input 42 of the initial installation of the scaling circuit 15 and the input of the asynchronous installation to the single state of the trigger 16 mode. As a result, the address register 7 is set

5 to the zero state; the address counter 43 {FIG. 2) scaling circuit 15 is in the zero state, and at the output of flip-flop 16 a signal arrives at the control inputs of the first 17 and second 18 switches, respectively. Thus, the first switch 17 provides the connection of the address bus 34 to the address inputs of blocks 11 and 12, the second switch 18 connects the data bus 33 to the data input of the memory block 12 of the address.processes.

The data bus 33 electrically has two states, although element outputs having three states are connected to it. This is due to the special inclusion of resistors that extend the third state on bus 33 to zero potential. At the time of the initial installation, none of the information sources are connected to the data bus 33, and the electric potential on it is zero. Therefore, when signals are written to the recording inputs of blocks 11 and 12, zeros will be written to the last. The recording signals for blocks 11 and 12 are generated at the time of a single potential at the second output of the synchronization unit 9, which is supplied to the second inputs of the AND elements 24 and 25, and removed from the outputs of these elements. As a result, the recording signal is fed to the recording input of the block 11 the memory of the addresses of processes from the output of the second element I 25 and to the input of the record of the block 12 pages memory from the output of the first element I 24.

The address of the entry is determined by the information on the address bus 34. The information on the address bus 34 is determined by the information found in the address register 7, in which zeroes appear at the initial setting signal. Therefore, the null information from the data bus 33 is recorded in blocks 11 and 12 at the zero address. This corresponds to the generation of the zero process. As soon as the existence of the write signals at the outputs of the first 24 and second 25 elements And terminates, blocks 11 and 12 are included in the read mode. At the output of the page memory block 11, the page number of the register memory block 10 corresponding to the spawned process appears. This number will be written into the register of 13 pages by the arrival at the second input of the fourth And 27 element of the signal from the first output of the synchronization unit 9, since the initial input of the And 27 element receives the initial setup signal from the output of the third element OR 31.

The information, recorded in the register of 13 pages, is fed to the input of the decoder 14 page numbers. The signal that occurred at one of its outputs is fed to the control input of the corresponding register memory block 10 and turns it on. At the same time, the block 12 of the memory of the addresses of the processes is also included in the reading mode and at its output appears information about

the first firmware address of the spawned process. This information is fed through the appropriately connected third switch 19 to the information input of register 2 of the firmware address, into which it is recorded upon arrival at the sync input of the sync signal 2 from the first output of the synchronization unit 9. Thereafter, the initial installation is considered complete, and the signal of the same name from output 35 is removed.

Then the microprocessor processor starts operating in the microprogram execution mode of the child, in this case, zero process. The loaded address of the microcommand from the output of the register 2 is fed to the input of the address of the block 3 of the memory of microcommands, at the output of which a parvah microcommand appears. The microcommand of this processor consists of four fields of microinstructions: the control field of the address of the next microcommand, the field of control microinstructions, the field of reading, the field of the operation code. Each micro-command from the output of the micro-command memory block 3 is inputted to the register of 4 micro-commands and is written to it by the arrival of a clock signal from its first output of the synchronization unit 9. One of the first microinstructions of the zero process must contain the microinstruction code Disconnecting the access mode in the field of control microinstructions. The control signal corresponding to this code after supplying this code to the input of the decoder 5 control microinstructions from the register output 4 micro-instructions appears on the same output of the decoder 5 and then goes to the synchronous input of setting zero of the mode trigger 16. The trigger 16 is set to zero when the clock signal arrives at its sync input from the first output of the synchronization unit 9.

The next microinstruction should provide information on the number of processes to be recorded in the scaling circuit 15. For this field, the operation code of the previous microcommand must contain a code that forms the corresponding information on the information output of the arithmetic logic unit 6. The subsequent micro instruction must contain a code in the reading field that allows reading information on the data bus 33 from the information output of the arithmetic. - a logical block 6, and in the field of control microinstructions the subsequent microinstruction must contain the code of microinstructions for recording the number of weights in a scaling circuit (Fig. 2). Information about

the number of processes from the data bus 33 goes to the information input 41 of the scaling circuit 15, and the write control signal is output from the Record of the number of processes in the scaling circuit of the decoder 5 control microinstructions to the input 40 of the number of processes of the scaling circuit 15. And the write signal is fed to the input Register 45 of the number of processes and provides for recording information from the bus 33 of data into it. After these mandatory microcommands have been completed, the processor can execute any microcommands due to the process being serviced. Similar to the generation of the zero process, the generation and subsequent processes occur. The difference is that, firstly, the mode trigger 16 is set to one state synchronously when a signal arrives at its input. Setting the mode from the corresponding output of the decoder 5 of the control microinstructions and to its sync input clock signal from the first output of the synchronization unit 9. The Signal Mode Setting appears at the same output of the decoder 5 when the corresponding code arrives at the input of the decoder 5 from the field of control microinstructions from the register 4 output of microcommands.

Secondly, the recording of information about the page number and the process address into blocks 11 and 12, respectively, is carried out separately by performing two microcommands. In the first micro-command, the corresponding code in the field of the operation code provides the appearance of information corresponding to the page number of the generated process at the information output of the arithmetic-logic unit 6. In the second micro-command, the corresponding code in the read field provides this information to the data bus 33, and the code in the field control microinstructions causes the appearance of the output Record page decoder 5 of the same signal. This signal through the second element OR 30 is fed to the first input of the first element AND 24 and permits the passage through the second input of this element from the second output of the synchronization unit 9 to the recording input of the page memory unit 11.

Thus, information from the data bus 33 is stored in the page memory unit 11. The second pair of micro-instructions similarly records the starting address of the process being spawned in block 12 of the process address memory. In the first micro-command, the corresponding code in the operation code field provides information that defines the initial microprogram address of the process being spawned at the information output of the arithmetic logic unit 6. In the second

to the micro-command, the corresponding code in the reading field ensures the issuance of this information to the data bus 33, and the code in the field of control microinstructions Causes an output on the Record of the address of the decoder 5 of the same signal. This signal through the first element OR 29 enters the first input of the first element AND 25 and permits the passage through the second input of this element from the second output 5 of the synchronization unit 9 to the input of the recording of the memory 12 of the process address memory.

Thirdly, the address of the entry in blocks 11 and 12 is determined in arithmetic logic unit 6 and appears at its output address.

0 In the next micro-command, this address is written into the register 7 of the address by supplying it to the information input of the register 7 and generating, according to the operation code, a signal to control the recording coming in

5 input synchronization register 7 addresses. This address from the output of register 7 is provided to the bus 34 of the address and from it goes to the address inputs of blocks 11 and 12 through the appropriately connected via

0 trigger 16 mode, the first switch 17. The address of the recording of information about the generated process is numerically equal to the addresses of the first empty cells in blocks 11 and 12, since writing to blocks 11 and 12 is always made

5 at the same addresses, the addresses of the first empty cells in these blocks are the same. In absolute value, the address of the first empty cells in blocks 11 and 12 corresponds to the contents of the register 45 of the number of processes (FIG.

0 2), since the count of the number of processes in the processor starts from one, the write address of the initial (zero) process is zero, and the record is made at sequential addresses. Getting

5, the address information of the first empty cell in blocks 11 and 12 is performed by performing a read operation.

A read operation provides information to the bus 33 of the process information

0 stored at an arbitrary address in blocks 11 and 12, and reading information about the conversion circuit 15. The read operation is implemented using the microcommand reading field. Microcommand Reading Field

5 has unitary coding and since it provides reading from six devices, it has a number of bits. The six devices served by the reading field are the informational bidirectional output of the arithmetic logic unit 6, the informational bidirectional output of the RAM unit 8 and, accordingly, the first 20, second 21, third 22 and fourth 23 bus drivers. Each bit of the reading field is connected to one of the listed devices. If it is necessary to read from any of these devices, there is a unit in the reading field connected to the required device.

Reading the information about the process occurs when the following sequence of microinstructions is performed. In the first microcommand in the control microinstruction field there should be a code ensuring the formation of a signal. Setting the mode on the same output of the decoder 5 control microinstructions. The Set mode signal is input to the synchronous setup of the mode trigger 16 in a single state, and on arrival at the sync input of the sync trigger 16 from the first output of the synchronization unit 9, a single signal is set at the output of the fig 16. It is fed to the control inputs of the first 17 and second 18 switches, respectively. Upon receipt of this signal, the first switch 17 will connect the address bus 34 to the address inputs of blocks 11 and 12 of the page memory and process addresses, respectively. The switch 18 connects the data bus 33 to the data input of the process address memory 12 block.1

In the second microcommand, the code of the operation code should contain a code that ensures the formation of the information reading address at the address and the write control signal at the same output of the arithmetic logic unit 6. The presence of these signals at the corresponding inputs of the address 7 will ensure the recording of the generated information reading address register 7, and from the last output, the reading address of the process information will go to the address bus 34. In addition, in the reading field of the second micro-command, there must be a code that provides reading information from the output of the bus driver 20 to the data bus 33. The information input of the bus driver 20 receives information from the output of the memory block 11, readable at this moment from the cell whose address is determined by the address bus 34, i.e. is contained in address register 7.

In order to consume the information read in such a manner, in the control microinstructions field of the same microinstruction, a code should be found that allows the decoder 5 control microinstructions to generate a signal on their own.

corresponding to the output signal Record in the memory block. This signal, which is fed to the input of the recording of the RAM block 8, will record information from the data bus 33 at the same address at which this information is read from the block 11 of the page memory. This is one of the possible ways to consume information read about the process. Similarly, the process address information is read from the process address memory unit 12. In the third microcommand, if the read information is consumed and no reading of information from other devices is required, the microinstruction code must contain a microinstruction code in order to form the Unlock mode on the corresponding output of the decoder 5. By this signal, the trigger 16 mode will be set to the zero state, and in the firmware the servicing process will remain the same process, the address of which is determined by the address output 36 of the scaling circuit.

By reading the information from the scaling circuit, you can output to the data bus 33 the address of the process currently in service, and the number of processes existing in the processor. To do this, you need to set the trigger 16 mode to one state by the first micro-command described above. The second micro-command must contain in the reading field a code corresponding to reading either the information from the output of the bus driver 22 or the information from the output of the bus driver 23. Accordingly, on the data bus 33 in the first case the address of the process that is in service appears, because to the information input bus former 22 connected address output 36 of the scoring circuit. In the second case, on the bus 33 of the data on Wits, the number of processes existing in the processor, since the output 37 is connected to the information input of the bus driver 23. The number of processes of the scaling circuit 15. The information from L data 33 data is consumed by the third micro-instruction or by the method indicated above by block 8 operating memory or arithmetic logic unit 6 provided that the third microcommand contains a corresponding code in the field of the operation code, which stores information from the data bus 33 through the information input to the arithmetic methico-logical unit 6.

The process can be set up for maintenance in two ways: cyclically in turn and arbitrariness (but at the specified address of the cells of blocks 11 and 12, respectively, of the pages and addresses of the processes that store information about the process.

The operation of putting the process into service is cyclically performed in turn by a sequence of two micro-instructions (diagrams in FIG. 6) that appear last in the previous process. In the first micro-command, the address of which is in register 2 of the microprogram address and which is read from block 3 of the memory of micro-commands (points 1 of the diagrams D and D of Fig. 6), the microinstruction code of the process switching is contained in the control microinstruction field. At the moment of reading this microcommand from block 3 of microcommand memory, the address output 36 of the scaling circuit (diagram L of Fig. 6) is connected via the first switch 17 to the address inputs of blocks 11 and 12. The information read from these blocks refers to the old one being serviced process. From the output of block 11, the address of the old process is read (diagram I of FIG. 6), and from the output of block 12, the page number (them) of the old process (diagram K of fig. 6). In the register, 13 pages are stored by it of the old process (diagram M of FIG. 6). With the appearance at the first output of block 9 of the next sync signal (diagram A of Fig. 6), the first micro-instruction is recorded in register 4 of micro-instructions (diagram E of Fig. 4), the field of control microstructures is fed to the input of the decoder 5, and the output appears Switching process (diagram G of Fig. 6). This signal is fed through the fourth element OR 32 to the control input of the third switch 19 and connects the output of the process address memory block 12 to the input of register 2 of the microprogram address. In addition, the signal Switching processes through the third element OR 31 is fed to the first input of the fourth element And 27, through the first element OR 29 to the first input of the second element And 25 and to the first input of the third element And 26.

At the output of register 2 of the firmware address, at this moment, the address of the second micro-command (point 2, diagram D of Fig. 6), which is read from the output of block 3 of the memory of micro-commands, is already found. The output of the block 3 is part of the bits corresponding to the address control field of the microcommand connected to the data input of the process address memory block 12 via the second switch 18. When a recording signal from the second output of the block 9 clock signal arrives at the write input of the block 12 25, block 12 will record the information from the field address control bits of the microcommand that define the new starting address (return point) for the old process (diagrams B, D, F, And Fig. 6). AT

the next moment of time appears a single signal at the third output of the synchronization unit 9 (diagram B of FIG. 6). He arrives at the second input element And 26, on the first input of which there is a signal

0 Switching the mode, so a signal comes from the output of the AND 26 element to the counting input 38 of the scaling circuit 15. This signal (Fig, 2) is fed to the counting input of the counter 43 of the address, which it increases

5 its contents per unit. A new address appears at output 36 of the scoring circuit and at the first input of circuit 44

The second input of the comparison circuit 44 is supplied with information from the output of the register 45

0 number of processes. If the new process address matches the number of processes stored in register 45, then comparison circuit 44 produces a signal. This signal is fed through the fifth element OR 46 to the input

5, the address counter 43 is set to zero, which means that the process queue is serviced, and a zero process is put back in service. In any case, at the output 36 of the address of the scaling circuit 15,

0 new address: zero or greater than one address of the old process (diagram L of Fig. 6). This address comes through the first switch 17 to the address inputs of blocks 11 and 12, from which the reading of the values of the name (page number) and starting address (return point) of the new process (I and K figures 6) begins. The page number of the new process, read from the output of memory block 11

0 pages, arrives at the information input of the register of 13 pages and is written into this register 13 upon arrival at the synchronous input of the register 13 of the next sync signal from the first output of the synchronization unit 9

5 (diagrams A, K, M of Fig. 6).

From the output of the register 13 pages of information is fed to the input of the decoder 14 page number. The forming signal at one of the outputs of the decoder 14 is supplied

0 to the control input of the corresponding page of the register memory block 10, and this page is turned on. The starting address of the new process, read from the output of the block 12 of the memory of the adres processes, goes through the respectively connected third switch 19 to the information input of register 2 of the firmware address and is written into this register 2 upon arrival of the next sync signal from the first output of the synchronization block 9 ( diagram A and D of Fig. 6). As a result, the start address of the new process will be sent to the address input of the microcommand memory block 3, the first microinstruction of which will begin to be read from the output of microcommand memory block 3 (diagrams D, D, point 3 in Fig. 6). With the next clock signal from the first output of the synchronization unit 9, the first microcommand of the new process is written into the register 4 of the microcommands (point 4, diagram E of Fig. 6) and its execution begins. A new process is considered as being delivered for service.

Setting the process for servicing not by waiting, but at the address of recording information about the sffcM process in blocks 11 and 12 occurs in the same way as putting on servicing by turns and is described by the same diagrams (Fig. 6), considering that in diagram E of Fig. Figure 6 shows the output signal. Recording the address in the scaling circuit of the decoder 5 control microinstructions, and microinstruction code. Recording the address in the scaling circuit is contained in the control microinstruction field of the first microcommand instead of the microinstruction code Switching processes.

In addition, in the first microcommand, the code of the operation code must contain a code that ensures that the information output of the arithmetic logic unit 6 contains the address of the process to be serviced; in the reading field, the reading code of the information output of the arithmetic logic unit 6 on the memory bus 33 . Then the signal Address writing to the scaling circuit appears at the output of the decoder 5 of the same name and goes through the first element OR 29 to the first input of the second element AND 25 and to the first input of the fifth element And 28 (point 2, diagram E in Fig. 6). The signal from the output of this element is 28 and Vits and will go to the input 39 of the recording of the address of the scaling circuit 15 at the time of the occurrence of a single signal at the third output of the synchronization unit 9. This signal is fed to the input of the record of the address counter 43 (FIG. 2) and records information from the information input 41 of the scaling circuit connected to the data bus 33 at which the address of the new process is found at that moment. As for the rest, the procedure for setting up a new process for servicing fully coincides with the previous one.

The process of destroying the process by pushing is performed using the operations of reading information about the process and spawning a new process. If it is necessary to destroy some process that is in a cyclic queue in the microprocessor processor, it is first necessary to set the mode trigger 16 to one state as indicated above. Then perform the operation of reading the name and 5 addresses of the process, information about which is recorded in blocks 11 and 12 of memory at the address following the address at which information about the process being deleted is recorded in blocks 11 and 12.

0 Next, an operation is performed to generate the process that was just read at the address of the process being deleted. Thereafter, the read address is incremented by one relative to the address at which the previous read operation was performed, and the process of generating the process, read by the second, is performed, at the address of the process, read by the first. The process of reading information about the process at the subsequent address and spawning this process at the previous address continues until all the processes that are in the queue for the process being deleted are overwritten. After that, the trigger 16 mode is translated to

5, the zero state, and a new, reduced by one, number of processes existing in the processor is recorded in the scoring circuit 15.

Claims (1)

Invention Formula 0 A firmware processor containing a firmware address generation unit, a firmware address register, a microinstruction memory block, a microcommand register, 5 control microinstructor decoder, arithmetic logic unit, address register, main memory unit, synchronization unit, main register memory unit, the microprogram address register register output connected to the first input of the microprogram address generation unit and microcommand memory block address input whose output is connected to the information input of the register 5 micro-commands, the synchronous input of which is connected to the synchronous input of arithmetic logic. unit, with the synchronous input of the register of the microprogram address and with the first output of the synchronization block, the output of controlling the microcommand register address is connected to the second input of the microprogramming address generation unit, the output of the microcontrol register is connected to the third input 5 of the firmware address generation unit and with the input of the decoder of the control microinstructions, the reading output of the microcommand register is connected to the input of the main memory block, the write input of which is connected to the data recording output control microinstructor decoder, the first output of the firmware address generation unit is connected to the transfer input of the arithmetic logic unit, the transfer output of which is connected to the fourth input of the microprogramming address generation unit, the fifth input of which is connected to the output of the operating memory unit and to the information input of the arithmetic logic input block, the input of the operation code of which is connected to the same output of the microcommand register, the output of the address of the arithmetic logic unit is connected to the information input p The address register whose sync input is connected to the recording control output of the arithmetic logic unit, the sync output of which is connected to the synchronous input of the main register memory block, whose information input-output is connected to the input-output of the register information of the arithmetic logic unit, the output of the register address of which is connected to the input addresses of the main register memory block, characterized in that, in order to improve performance by reducing the time when switching from process to process to multiprogram In many operating modes, additional register memory blocks, a page memory block, a process address memory block, a page register, a page decoder, a scaling circuit, a mode trigger, first, second and third switches, first, second, third and fourth are entered into it. bus drivers, first, second, third, fourth, and fifth elements AND, first, second, third, and fourth elements OR, and the synchronous inputs of additional blocks of the register memory are connected to the synchronized output of the arithmetic logic unit It is connected to the address inputs of additional register memory blocks, the information inputs / outputs of which are connected to the input-output of the register information of the arithmetic logic unit, whose information input is simultaneously an information output and connected to the information input of the RAM memory block, which is Its information output, connected to the data bus, to which the information input of the scaling circuit is connected, outputs, respectively, the first, second, third and fourth bus forms the first information input of the second switch and the data input of the memory of the pages, the output of which is connected to the information inputs of the first block of bus drivers and the register of pages, the output of which is connected to the input of the page decoder, the outputs of which are connected respectively to the control inputs of the main and additional blocks of the register memory, the address output of the scaling circuit is connected to the information input of the third bus driver and the first information input of the first switch, the output to torogo coupled to address inputs of memory pages block and a block address memory processes, the output of which is connected to the data input of the second 5 bus driver and with the first information input of the third switch, whose input is connected to the information input of the register of the microprogram address, the second information input 0 of the third switch is connected to the second output of the firmware address generation unit, the control input of the third switch is connected to the output of the fourth OR element, the first input of which is connected to the initial setup input of the processor, to the first input of the third OR element, to the single input of the mode trigger, to the input the initial setup of the address register, with the first input of the second OR element, with the input of the initial installation of the scaling circuit and with the first input of the first OR element whose output is connected to the first input of the input unit And, the output of which is connected to the input of the recording of the memory of the process addresses, the data input of which is connected to the output of the second switch, the second information input of which is connected to the output of the microinstructions memory, the control input of the second switch is connected to the output of the mode trigger and with the control input of the first switch, the second information input of which is connected to the address bus to which it is connected 5 the output of the address register and the input of the address of the RAM block, the read input of which is connected to the read input of the arithmetic logic unit and to the control inputs of the first, second, third, and 0 of the fourth bus driver, the information input of which is connected to the output The number of processes of the counting circuit, the counting input of which is connected to the output of the third And element, the first input 5 of which is connected to the second inputs of the first, third and fourth elements OR, respectively, and to the switching output of the processes of the decoder of the control microinstructions, the output of which the mode is set to be connected to the second unit the setup input of the mode trigger, the zero setup input of which is connected to the output of the decoder mode control microinstructions, the output of the page recording of which is connected to the second input of the second OR element, the output of which is connected to the first input of the first memory element these pages, the second input of the first element And is connected to the second input of the second element And and the second output of the synchronization unit, the third output of which is connected to the second input of the third element And and the first the input of the fifth element And, the output of which is connected to the input of the record of the address of the scaling circuit, the input of the record of the number of processes of which is connected to with the same name output of the control microinstructor, the output of writing the address of the scaling circuit of which is connected to the second input of the fifth AND element, to the third input of the third OR element, to the third input of the fourth OR element, and to the third input of the first OR element, the fourth input to which is connected to the recording output addresses of the process of the decoder control microinstructions, the output of the third element OR is connected to the first input of the fourth element AND, the output of which is connected to the synchronous input of the page register, the second input quarter Element element I is connected to the first output of the synchronization unit and to the synchronous input of the mode trigger. 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