SU417896A1 - - Google Patents

Description

one

The invention relates to the field of computing and can be applied as a functional element in automatic control and monitoring systems.

A device is known that contains a binary counter, an encoder, a circuit and a trigger control, coefficients and delay lines.

However, such a device does not provide for the multiplication of signals of a continuous impulse sequence by the coefficients, men1) of a unit.

The purpose of the invention is the multiplication of pulse signals, iia fractional coefficients.

This is achieved by the fact that in the device the source of the pulse sequence is connected to the counter input and to the first input of the AND circuit, the second input of which is connected to the zero output of the control trigger and through the first delay line and the first capacitor to the first input of the encoder, and the single output of the control trigger through vtorueOO delay line and the second capacitor is connected to the second input of the encoder, the outputs of which are connected to the single inputs of the meter triggers, and the zero inputs of the meter triggers and the control trigger trigger are connected to the terminal “Original.

The drawing shows a diagram of the proposed device.

The device consists of a binary counter 1 on n triggers 2, trigger 3 on control, delay lines 4 and 5, capacitors 6 and 7, encoder 8, for example on diodes, and control key 9 performed on the "I.

The pulse sequence signal U is applied to the counting input of trigger 2 of the lower bit of the binary counter 1 and the control key 9. The unit output of trigger 2 of the higher bit of counter 1 is connected to the counting input of trigger 3 of control, the zero output of trigger of control — with input of switch 9 and through delay line 4 and capacitor 7 s

one input of the encoder 8, and the outputs of the encoder with single inputs of the trigger 2 of the counter 1. The output circuit of the coma. The source is connected to the zero inputs of the trigger 2 of the binary counter and the control trigger.

From the output of the key 9, the transformed sigpal is removed.

The device works as follows. When issuing the command “Initial Triggers 2 of Counter 1 and Control Trigger 3, go to the initial (zero) state. At the same time, at the zero output of the control trigger, a signal is generated that opens the key 9 and, through the delay line 4, the capacitor 7, the encoder 8 delivers the effect to a single

the inputs of the triggers 2 of the counter 1 in the form of a parallel binary code expressing the addition D1. By the command “Start-up, the signals of the pulse sequence U are fed to the input of the counter 1 and the input of the key 9. Since by the command“ The source key is opened, the pulses go through it to the output of the device.

When counting pulses at the output of counter 1, an overrun command is generated, according to which the control trigger goes to one state and the key is closed. A signal appears on the unit control trigger output, which, via delay line 5, co-detector 6, encoder 8, is fed to the unit inputs of trigger 2 of counter 1 in the form of a binary code corresponding to appendix D2. Thus, the installation of counter 1 in the initial position and the subsequent introduction of the supplement D2 through the delay line and the listed elements is carried out in the time interval between m and m - | -1 pulses. With the arrival of the m + 1-ro pulse, the counter starts the чет odd burst (k-m) given by the D2 addition. In this case, the pulses are not removed from the output of the device, so: As the key is closed.

When counting a pack of (k-t) pulses, an overflow command is generated at the output of the counter. By this command, the trigger trigger is switched to the zero state and the key opens from the zero output and enters the D1 completion into the counter. With the input of the (k-m) + l-ro pulse, the cycle is repeated.

Thus, when signals of the pulse sequence are received at the input of the device, periodically m pulses from k are transmitted by the device and (k-m) pulses from k are cut off.

The considered cycle of transmission and cut-off of pulses is carried out at intervals of i / g imiuls.

If a unitary code (burst of pulses) is applied to the input of the device instead of a continuous stream of pulse sequence, expressing the measured parameter with the number of pulses jV, then a new unitary NI code with the number of pulses is formed on the output of this device.

-.

If in fractional ratio - 1 for

give a constant value of m, then the device performs the functions of a pulse sequence signal divider with a multiplicity of 2, 3 ...

Subject invention

A device for multiplying pulsed nosledity signals, comprising a binary counter, an encoder, a circuit and a trigger trigger, capacitors and delay lines,

characterized in that, in order to multiply the pulse signals by fractional coefficients, the source of the pulse sequence is connected to the counter input and to the first input of the P circuit, the second input of which is connected to the zero output of the control trigger and through the first delay line and the first capacitor is connected to the first input the encoder, the unit output of the control trigger via the second delay line and the second capacitor is connected to the second input of the encoder, the outputs of which are connected to the unit inputs of the meter triggers, and zero The second inputs of the trigger trigger and the control trigger are connected to the terminal "Original.