SU720427A1 - Digital integrator - Google Patents

Description

The device relates to computing devices of control systems and can be used in numerical software control systems of various technological equipment. The integrator 1 is known, it contains a counter for the integrand, a clock counter and a combination unit consisting of AND-OR cells. The drawback of the device is that the volume of the combinational block increases in proportion to the number of its bits. The closest technical solution to the invention is the integrator of the digital d1-differential analyzer 2, which contains the transform block of the integrand function, the first AND element, the iteration block, the shift register, the adder, the first input of which is connected to the output of the shift register, the first output to the shift input the register, the second output is the “time delay” element to the first input of the second element And connected by the output to the second input su #;; ztoro, and the left input to the output of the DTC iterator block The fact that the volume of the transform block of the integrand increases in proportion to the number of its bits, which reduces the reliability of the entire device. The purpose of the invention is to enhance. reliability of the integrator. The goal is achieved by the fact that in the proposed device the first input of the first element I is connected to the first output of the adder. The second input of the first element And is connected to the output of the shift register. The third input of the first element AND is connected to the output of the transform block of the integrand, and the third input of cyNiMaTopa is connected to the output of the iteration block. The drawing shows a block diagram of an integrator. It contains the transform block of the integrand function 1, the element AND 2, the block of iterations 3, the shift register 4, the control switch 5, the element of delay 6 and the element 7. 7. The integrator works as follows.

the iteration goes through n clock cycles, where n is the number of bits of block 1 and register 4, the increments L y Hut are fed to the inputs of block 1 and block iterations 3 in the first iteration cycle, when the second input of register 4 is fed to the second input, in which the value of the current time t is stored. In block 1, at the end of each iteration, the current value of the integrand

YW 2: dUa), fc.i

and in shift register 4 (with zero initial value), the current time value

t Z: flt (k).

Km

If at a certain iteration cycle at the output of register 4 by wils O and at the first output of adder 5 it has formed, then the element And 2 is unlocked and passes the next value to the output of the device from block 1

Jl (t).

On a sequence of iterations, 2, 3, 4 ... the output stream of increments forms a stream of frequency

 H

.Y.-Z

bt

Organizing and generating the output signal of the proposed integrator is similar to generating the output signal in a binary multiplier, where a special program counter, using a combinational circuit, which is a ruler of AND elements, polls the state of the bits of the register of the integrand function by a special program and outputs a pulse stream to the device output kind of

YYYXYYYY

I 2 I I I G. 4 4-- where Y I is the contents of the i-th bit of the register of the integrand function (YI is the highest bit). The program counter when integrated by the same and TOMi parameters can be common to several integrators. It has a combinational circuit, the volume of which increases with the number of bits n.

Thus, the introduction of new links between the blocks included in the integrator, has enabled

select the volume of non-standard combinational cxeNSJ, which does not increase with the number of bits;

when using a large number of integrators integrating over the same parameter, reduce the number of n-bit shift registers to one, and thereby increase the instrumental reliability of the integrator.

Claims (2)

1. US patent 2910237, cl. 135-150.3, 1959. 2.Shileyko A.V. Digital models. KL., Energie, 1964, p. 27.