TH6559B - A microcomputer system that uses a position compensation mechanism to increase the capacity of secret memory that can be supported. - Google Patents

Abstract

Increasing the capacity of the secret memory that the secret memory controller can support. This can be achieved by shifting the relationship between the processor output signal terminal and the input signal terminal of the secret memory controller and by doubling the size of the secret memory line accordingly in some case An additional logic device creates a hidden memory loop to retrieve a number of bytes equal to the size of the new line size from memory regardless of the width of the data line. A false memory read causes a hidden memory cycle to be initiated, and another logic device generates a memory location signal that the processor does not generate. The hidden memory controller cannot see the hidden memory cycle because the READY signal is inhibited from changing until the end of the hidden memory cycle and both normal memory cycles.

Claims (4)

1.Multi-cable type microcomputer system consisting of The central processing unit and the secret memory subsystem, which are connected to each other by means of the local processor cable. The secret memory subsystem consists of a confidential and secret memory control device. The system cable factor connects the secret memory controller circuit to a number of randomly executable memory and addressable operations. In the event that the processor has an output channel of the processor and the control device, the said secret memory has the input and Factors, which connect some of the processor's output channels to the input channels of some of the said secret memory controllers, cause some of the said exit channels of the processor. Say some channels with the signal of the input channel does not match. 2. The multi-wire microcomputer system described in Claim No. 1, which also consists of The logic factor for generating a position signal that generates a position signal into such randomly executable memory. And the factor which will connect at least one such central processor output channel to the logic factor for generating such position signal. 3. Multi-line microcomputer system as described in the claim. Article 1 or No. 2 in the case of the secret memory control device such chicken, the secret memory controller 82385 and in the case of the unit The secret memory has a capacity of at least 64 kilobits. 4. Multi-wire microcomputer system as described in Clause 2 in case of position signal input which is a logical factor for generating position signal. It generates to such randomly executable memory different from the position signal at the unit's output position channel. 5. The multi-line microcomputer system as described in Clause 1, which also consists of The logic factor for generating position signals, which generates position signals, enters the secret memory. And the factor which will connect at least one such central processor output channel to the logic factor for generating such position signal. 6. Multi-line microcomputer system as described in the claim. Article 5. In the event that the logic factor for generating such position signals will also generate a position signal into the aforementioned randomly executable memory. 7. Multi-wire microcomputer system as described in paragraph Clause 6 is held in the event that the position signal which the logic factor for generating such position signal has been generated to such random executable memory differs from the position signal at the unit's exit position signal. 8. A multi-wire microcomputer system as described in Clause 5, in the case of a position signal which the logic factor for generating such a position signal is created to the secret memory. Such signal differs from the position signal at the output channel of the aforementioned processor. 9. Multi-line microcomputer system. Which consists of The central processing unit and the secret memory subsystem, which are connected to each other by means of the local processor cable. The secret memory subsystem consists of devices Control the 82385 secret memory and the secret memory. The central processing unit contains the output channel of the processor. The factor which connects some of the said processor output channels to the aforementioned 82385 secret memory controller's input channels, such as the 82385 that the processor output channels are connected to the position channels. 82385 Secret Memory Controller Unmatched Channel Factor 82385 System Line Factor, which connects the aforementioned 82385 Secret Memory Controller circuit to a randomly executable memory and capable operating unit Position Get a certain amount The logic factor for generating position signals, which generates position signals, enters the secret memory. The factor which will connect at least one such central processing unit's output channel to the logic factor for generating that position signal. And the factor which will connect the output position signal Of the central processing unit with the secret memory. In the event that the aforementioned secret memory has a capacity of at least 64 kilobits 1 0. Multi-wire microcomputer system as described in Claim 9, in case of position signal which factor The logic for generating such a position signal to the aforementioned memory differs from that of the position signal at the output channel of said processor 1. 1. A multi-wire microcomputer system as described in Clause 9, where the logic factor for generating such a position signal will generate a position signal into a randomly executable memory. Such 1 2. A multi-wire microcomputer system as described in Proposition 11, in the event of a position signal which the logic factor for generating such a position signal is generated to a randomly executable memory. They differ from position signals. At the output channel of the unit Central processing thereof 1 3. The multi-wire microcomputer system, as described in Claim 11 or No. 2, also contains hidden cycle initiation factors that are connected to the said processor and to the device. It controls the secret memory and reacts to the false memory read cycle that the secret memory controller has identified by creating a hidden memory read cycle 1. 4.Multi-wire microcomputer system as described Claim No. or No. 2, in the event that the output port of A3 to A30 processor is connected to the input channel CCA2 through CCA29 of The device controls the said memory. And the output position signal of the A2 processor is connected to the logic factor for generating such a position signal.