TW199236B - - Google Patents
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- Publication number
- TW199236B TW199236B TW080104126A TW80104126A TW199236B TW 199236 B TW199236 B TW 199236B TW 080104126 A TW080104126 A TW 080104126A TW 80104126 A TW80104126 A TW 80104126A TW 199236 B TW199236 B TW 199236B
- Authority
- TW
- Taiwan
- Prior art keywords
- impurity diffusion
- diffusion region
- patent application
- semiconductor
- impurity
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
- H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0147—Manufacturing their gate sidewall spacers
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910004394A KR940000510B1 (ko) | 1991-03-20 | 1991-03-20 | 반도체 메모리장치 및 그 제조방법 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW199236B true TW199236B (ja) | 1993-02-01 |
Family
ID=19312269
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW080104126A TW199236B (ja) | 1991-03-20 | 1991-05-27 |
Country Status (7)
| Country | Link |
|---|---|
| JP (1) | JP2564712B2 (ja) |
| KR (1) | KR940000510B1 (ja) |
| DE (1) | DE4117703C2 (ja) |
| FR (1) | FR2674373B1 (ja) |
| GB (1) | GB2253937B (ja) |
| IT (1) | IT1247968B (ja) |
| TW (1) | TW199236B (ja) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6258671B1 (en) | 1997-05-13 | 2001-07-10 | Micron Technology, Inc. | Methods of providing spacers over conductive line sidewalls, methods of forming sidewall spacers over etched line sidewalls, and methods of forming conductive lines |
| DE10121011B4 (de) * | 2001-04-28 | 2004-11-04 | Infineon Technologies Ag | Verfahren zur maskenlosen Kontaktlochdotierung bei DRAMs/eDRAMs und entsprechend hergestellter Speicherchip |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4364075A (en) * | 1980-09-02 | 1982-12-14 | Intel Corporation | CMOS Dynamic RAM cell and method of fabrication |
| JPS60164570A (ja) * | 1984-02-06 | 1985-08-27 | 株式会社東芝 | 扉ロツク装置 |
| JPS61156962A (ja) * | 1984-12-27 | 1986-07-16 | Nec Corp | 構内電子交換システム |
| JPS61156862A (ja) * | 1984-12-28 | 1986-07-16 | Toshiba Corp | 半導体記憶装置 |
| JPS61218165A (ja) * | 1985-03-25 | 1986-09-27 | Hitachi Ltd | 半導体記憶装置及び製造方法 |
| JPH0821682B2 (ja) * | 1987-04-24 | 1996-03-04 | 株式会社日立製作所 | 半導体装置の製造方法 |
| JP2810042B2 (ja) * | 1987-09-16 | 1998-10-15 | 株式会社日立製作所 | 半導体集積回路装置 |
| JPH01231364A (ja) * | 1988-03-11 | 1989-09-14 | Hitachi Ltd | 半導体集積回路装置 |
| JPH0821687B2 (ja) * | 1989-05-31 | 1996-03-04 | 富士通株式会社 | 半導体装置及びその製造方法 |
| JP2673385B2 (ja) * | 1989-10-26 | 1997-11-05 | 三菱電機株式会社 | 半導体装置 |
| DE4034169C2 (de) * | 1989-10-26 | 1994-05-19 | Mitsubishi Electric Corp | DRAM mit einem Speicherzellenfeld und Herstellungsverfahren dafür |
-
1991
- 1991-03-20 KR KR1019910004394A patent/KR940000510B1/ko not_active Expired - Lifetime
- 1991-05-27 TW TW080104126A patent/TW199236B/zh not_active IP Right Cessation
- 1991-05-30 FR FR9106512A patent/FR2674373B1/fr not_active Expired - Fee Related
- 1991-05-30 DE DE4117703A patent/DE4117703C2/de not_active Expired - Lifetime
- 1991-06-04 IT ITMI911513A patent/IT1247968B/it active IP Right Grant
- 1991-06-05 GB GB9112136A patent/GB2253937B/en not_active Expired - Lifetime
- 1991-06-20 JP JP3148392A patent/JP2564712B2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| KR940000510B1 (ko) | 1994-01-21 |
| JPH04320059A (ja) | 1992-11-10 |
| DE4117703A1 (de) | 1992-09-24 |
| JP2564712B2 (ja) | 1996-12-18 |
| GB2253937A (en) | 1992-09-23 |
| GB2253937B (en) | 1995-10-25 |
| ITMI911513A0 (it) | 1991-06-04 |
| GB9112136D0 (en) | 1991-07-24 |
| FR2674373A1 (fr) | 1992-09-25 |
| KR920018890A (ko) | 1992-10-22 |
| FR2674373B1 (fr) | 2001-07-06 |
| ITMI911513A1 (it) | 1992-12-04 |
| IT1247968B (it) | 1995-01-05 |
| DE4117703C2 (de) | 1994-12-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MK4A | Expiration of patent term of an invention patent |