TW200735101A - Random cache read using a double memory - Google Patents

Random cache read using a double memory

Info

Publication number
TW200735101A
TW200735101A TW095149754A TW95149754A TW200735101A TW 200735101 A TW200735101 A TW 200735101A TW 095149754 A TW095149754 A TW 095149754A TW 95149754 A TW95149754 A TW 95149754A TW 200735101 A TW200735101 A TW 200735101A
Authority
TW
Taiwan
Prior art keywords
memory
volatile memory
cache read
core array
double memory
Prior art date
Application number
TW095149754A
Other languages
English (en)
Other versions
TWI351034B (en
Inventor
Nancy Leong
Sachit Chandra
Hou-Nien Chen
Original Assignee
Spansion Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Spansion Llc filed Critical Spansion Llc
Publication of TW200735101A publication Critical patent/TW200735101A/zh
Application granted granted Critical
Publication of TWI351034B publication Critical patent/TWI351034B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20—Employing a main memory using a specific memory technology
    • G06F2212/202—Non-volatile memory
    • G06F2212/2022—Flash memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
TW095149754A 2006-01-17 2006-12-29 Random cache read using a double memory TWI351034B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/332,241 US7423915B2 (en) 2006-01-17 2006-01-17 Random cache read using a double memory

Publications (2)

Publication Number Publication Date
TW200735101A true TW200735101A (en) 2007-09-16
TWI351034B TWI351034B (en) 2011-10-21

Family

ID=37963902

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095149754A TWI351034B (en) 2006-01-17 2006-12-29 Random cache read using a double memory

Country Status (3)

Country Link
US (1) US7423915B2 (zh)
TW (1) TWI351034B (zh)
WO (1) WO2007084217A1 (zh)

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US8370603B2 (en) * 2008-12-23 2013-02-05 Apple Inc. Architecture for address mapping of managed non-volatile memory
US20100287329A1 (en) * 2009-05-06 2010-11-11 Apple Inc. Partial Page Operations for Non-Volatile Memory Systems
US8321647B2 (en) 2009-05-06 2012-11-27 Apple Inc. Multipage preparation commands for non-volatile memory systems
US8438453B2 (en) 2009-05-06 2013-05-07 Apple Inc. Low latency read operation for managed non-volatile memory
JP2011014205A (ja) * 2009-07-03 2011-01-20 Renesas Electronics Corp 不揮発性半導体記憶装置
US8495332B2 (en) * 2009-07-24 2013-07-23 Apple Inc. Controller for optimizing throughput of read operations
TWI435215B (zh) * 2009-08-26 2014-04-21 Phison Electronics Corp 下達讀取指令與資料讀取方法、控制器與儲存系統
US8489907B2 (en) * 2009-09-16 2013-07-16 Apple Inc. Method of selective power cycling of components in a memory device independently by reducing power to a memory array or memory controller
US8838877B2 (en) * 2009-09-16 2014-09-16 Apple Inc. File system derived metadata for management of non-volatile memory
US9892032B2 (en) * 2013-02-07 2018-02-13 Sandisk Technologies Llc Management of random cache read operations
CN103824582A (zh) * 2014-03-26 2014-05-28 贵州大学 一种可拆分双存储u盘
US10977121B2 (en) * 2018-10-17 2021-04-13 Macronix International Co., Ltd. Fast page continuous read
US11048649B2 (en) 2018-10-17 2021-06-29 Macronix International Co., Ltd. Non-sequential page continuous read
US10957384B1 (en) 2019-09-24 2021-03-23 Macronix International Co., Ltd. Page buffer structure and fast continuous read
US11249913B2 (en) 2020-03-06 2022-02-15 Macronix International Co., Ltd. Continuous read with multiple read commands
US11302366B2 (en) 2020-03-06 2022-04-12 Macronix International Co., Ltd. Method and system for enhanced read performance in low pin count interface

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Also Published As

Publication number Publication date
US7423915B2 (en) 2008-09-09
WO2007084217A1 (en) 2007-07-26
US20070165458A1 (en) 2007-07-19
TWI351034B (en) 2011-10-21

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