TW201211771A - Asymmetric transport system and method of heterogeneous dual-core - Google Patents

Abstract

Asymmetric transport system and method of heterogeneous dual-core are provided. The asymmetric transport system includes a general purpose processor, a shared memory, a mailbox, and a coprocessor that differents from the kind of the general purpose processor. The shared memory is coupled between the general purpose processor and the coprocessor. The mailbox is also coupled between the general purpose processor and the coprocessor. The general purpose processor writes a first data to the shared memory. The coprocessor reads the first data from the shared memory, and does calculation processing on the first data, and gets a second data, and then writes the second data to the mailbox, wherein information flow of the second data is much smaller than information flow of the first data. The mailbox finally transmits the second data to the general purpose processor. The invention can save the source of memory and the using of hardware interrupts.

Description

201211771 wu*t-ii/-vi〇35295twf.doc/I VI. Description of the Invention: [Technical Field] The present invention relates to a dual core transmission system and method, and in particular to a heterogeneous dual core Asymmetric transmission systems and methods. [Prior Art] In the prior art, communication between common dual core processors is a symmetrical transmission mechanism. For example, Texas Instruments' DaVinci handles the architecture of the Advanced RISC Machine (abbreviated as ARM) and the core of the Digital Signal Processor (DSP). Using the shared memory method to do the bidirectional transfer of data, first divide the shared memory into two memory blocks ARM-to-DSP and DSP-to-ARM, when the ARM core transmits data to the memory block ARM After -to-DSP, the DSP core needs to be notified by interrupt to read the ARM-to-DSP data of the memory block. Conversely, after the DSP core transmits the data to the memory block DSP-to-ARM, it needs to pass through The interrupt informs the ARM core to read the data of the memory block _DSP-to-ARM. In the traditional data transmission method, the ARM core writes data to the memory, the DSP core reads the memory data, the DSP core writes the data to the memory, or the ARM core reads the memory data, and must use the interrupt to communicate. . Traditional technology shares memory for two-way communication, and hardware interrupts are required regardless of the amount of traffic transmitted, thus wasting memory usage and hardware interruption.

-ulO 35295twf.d〇c/I 201211771 SUMMARY OF THE INVENTION The present invention provides a morning symmetry transmission system that does not require bidirectional and symmetrical transmission systems. This non-data transfer is done to save the memory ==:: to the shared memory. The present invention provides for the use of hardware interrupts. The asymmetric transmission method does not require a dual asymmetric transmission method, and this resource = upper memory device = shared memory. Connect to shared memory. Collaborate on the hidden body. Coprocessor coupling 2; τ to the first, :==== Processor and co-processing The transfer from the mailbox to the general processing ^ a data system is first written to the mailbox, and then called the corner said 3:;! One! The quality of the dual core is not the same as the 3 material = the input method includes the following steps: · General processing - data · reading body; off processing 11 reading the shared capital from the shared memory _ on the first - turn to do # processing, to get ^ 4 'The coprocessor writes the second data to the mailbox, the second ^

*〇 35295twf.doc/I 201211771 Data flow less than the first data is transferred to the general purpose processor. The claws, and the mailbox will be second. In an embodiment of the present invention, the -direction is the same as the volume, and is written by the coprocessor to the shared memory shared memory by the shared processor (4). The direction will be the same as the amount of data in the n-th "data" cannot be retrieved from the processor JL and cannot be retrieved from the coprocessor f to the shared memory, where the amount of data referred to is the amount of data written. The amount of money is equivalent or similar to the first - f - in the embodiment, the second capital - direction, only by the coprocessor (four) u direction for the general purpose processor to read the second person from the mailbox to the mailbox 'and by The same amount of information in the second data is returned: synergy, the mailbox will be in the opposite direction, the device will be the same amount of information in the second data, the same amount of data is equivalent or _ second (four) of the information ^ small touch in the invention Finance, on =; ': the flag of the flag register, the second access authority, "money_ from the pure and read end of the bit processor, the above-mentioned general-purpose processor and the way to coordinate Use shared memory, where the general processing is based on the flag of the flag register The flags flag register contents do synergistic read at a glance embodiment of the present invention, the above-described first data surface is a day,

201211771 ~ l〇35295twfdoc/I 2 with the J processor is for the second data is the exact part of the local pattern in the face: set detection, f: in an embodiment of the 'first data analysis above Ratio = = adjacent two pictures in the continuous picture: The operation of the co-processor is to make the second data of the voice data as the compressed voice data. In the embodiment of the present invention, the operation of the first co-processor is to compress the file, the compressed file, and the compressed file. The first data is sent to the mailbox by the outgoing processor to the general processing. The second write = read command ^ two =====, passed to the processor through the shared memory. The coprocessor pair = two, the different processing, to obtain a part of the data in the large amount of data. Then pass the mailbox to the general purpose processor. The system of the present invention is asymmetric in the data flow transmitted by the two processors, and does not need to use the shared memory for data transmission, which can save the use of the source and the hardware interrupt. The above-described features and advantages of the present invention will become more apparent from the following detailed description. Special 7

35295 twf.doc/I 201211771 [Embodiment] In the following embodiments, when an element is referred to as a "connected" or "slightly connected" to another element, it may be directly connected or lightly connected to another element, or There may be components in between. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Please refer to FIG. 1. FIG. 1 is a block diagram of a heterogeneous dual-core asymmetric transmission (asynchr〇n〇us transfer) system according to an embodiment of the present invention. The asymmetric transmission system (8) includes a shared memory 110, a general purpose processor (generalpUrp〇sepr〇cess〇r) Gpp, a coprocessor CP, and a mailbox 120. The heterogeneous dual cores are two different types of processors, i.e., the type of the coprocessor CP is different from the type of the general purpose processor GPP. The general-purpose processor GPP can have a processing function for executing a general application (appiicati program), mainly control orientation, such as processing user interface, interrupt processing, and the like. The coprocessor cp is mainly used for mathematical operations, negative and immediate, with regular violations to cope with high computational requirements, such as fast Fourier transform, matrix multiplication, and so on. The coprocessor CP can be a digital signal processor (DSP), a % gateable array (e Gate Array 'abbreviated as FPGA) processor, or a complex programmable logic device (complex programmable logic device). Device, referred to as CPLD). In the above, the shared memory 110 is coupled between the general purpose processor Gpp and the coprocessor CP. The mailbox 120 is also coupled to the general purpose processor GPp and

ϋ 10 35295twf.docA 201211771 between the coprocessor CPs, the general-purpose processor GPP can receive the first data DATA from an external data capture device (not shown) or from the graphical user interface (graphical user interface, Referred to as GUI) Received the first data. The general-purpose processor GPP writes the received first data DATA1 to the shared memory coprocessor cp and reads the first data DATA1 from the wave-capable memory 110, and reads the first data DATA1.

A mathematical operation is performed to derive the second data DATA2, and then the first data DATA2 is written to the mailbox 120. Finally, the mailbox 12 transmits the first data DATA2 to the general purpose processor Gpp. The value of this system's transmission mechanism: (1) the first DATA1 data direction is transmitted in a single direction (as indicated by the thick arrow) in the single-direction by the processor Gpp to write the person--shared memory Volume 11G, unable to return from the shared memory m to the data of the first data DATA1 to the general processing, j the same amount of data referred to herein is equivalent or similar to the processor cp only from the shared memory 1 = - 枓 枓 DATA1, can not write from the coprocessor cp. = material DATA1 data to the shared memory m; data DATA2 data traffic transmission second indication) 'only in a single-direction by the coprocessor CP side DATA2 to mailbox 120, can not be your new Di 〇 〇, trojan into the second data two data DATA2 data and then return two ^ ^ will be the same amount of the same amount of information refers to the equivalent or classifier CP 'where the size And (4) General Processing Tm-2 data piracy GPP only reads from the mailbox 120 苐 2

35295twf.doc/I 201211771 Data DATA2 'Cannot write data from the sigh (4) Gpp to the mailbox 120. First poor material: Note that 'in this asymmetric transmission system 1 共有 shared direction (as indicated by thick and thin arrows), the first data general processor GPP via shared memory UG to the collaborative processor ^ From the first data flow direction is from the coprocessor cp via the general office (four) GPP's towel_--------------------------------------------------------- The technical solution that the traffic is much smaller than the demand of 2 can provide a more efficient transmission mechanism. St. Communication uses shared memory 11G for data transmission, which can be used as memory resources and hardware interrupts. 3 f Referring to FIG. 2, FIG. 2 is a diagram of a shared memory ιι 依 according to an embodiment of the present invention. Initially, it can be in the shared memory UG_ a flag register (Flag Registers) FR, as shown in the flag register FR has 16 _ flag content, can be used for domain: write Permission, read permission, write start position of the memory and end position of the read memory 0 For example, the first byte can be defined as discriminating the write permission of the general purpose processor Gpp or the read permission of the coprocessor CP. When the ith _ value is 〇, the processor GPP can write the shared memory n〇, and the cooperative processing H CP cannot read the shared memory 11G (4), when the i 201211771

Wwiv-010 35295twf.doc/I When the byte value is 1, the coprocessor CP can read the shared data] and the processor GPP cannot write the shared memory. 10 2~4 bytes can be defined as storing the general-purpose processor Gpp write 妓, the starting position of the memory 110, and the 5th to 7th bytes can be defined as the termination position f of the shared memory 110 written by the processor GPP. 『A byte can be defined as a storage coprocessor cp read record 2 10 position: the first i Μ 3 bytes can be defined as the storage coprocessor ^^

Take the end position of the co-dry memory 110, and the other byte retains its function. It is worth mentioning that the flag content of the flag register FR is an optional embodiment, and those skilled in the art can also change the byte size and content according to their needs. It is known that the general purpose processor GPP and the coprocessor cp can use the shared memory 11 上 to query the flag value of the flag register FR. For example, the processor GPP can perform the action according to the flag content of the flag register FR, and the coprocessor CP can perform the reading operation according to the flag of the flag register FR. For example, at the beginning, the general-purpose processor Gpp reads the first byte of the flag FR. If the first byte value is 〇, the general-purpose device GpP can write to the shared memory 110, and starts to transfer a large amount of data. = Material (such as the first data DATA1) is written into the shared memory 11〇, after the direct write, the first byte value of the flag register FR is changed to wide to allow the coprocessor CP to perform the read operation. . That is, when the general-purpose processor GPP writes the first data DATA1 to the shared memory 110, the coordinator 只需> only needs to perform the polling action, and checks the work site at intervals.

201211771 w.O 35295twf.doc/I byte ‘Check if the action can be read. When the coprocessor CP polls, the ball recognizes that the first byte value of the flag register fr is 1, and reads the data of the shared memory 11〇 until the read operation is completed, and then flags the flag. The first 1)^6 value of the scratchpad FR is changed to 0 to allow the general purpose processor Gpp to write to the shared memory. It is worth mentioning that, since the work of the coprocessor Cp only performs the mathematics, the usual idle time is to wait for the first data DATA1 transmitted by the general processor Gpp, and to transfer the second data DATA2 to the general data. Processor GPP. This method of polling does not use the interrupt command, and the mathematical operation of the coprocessor cp can be prevented from being interrupted and the original operation can be stopped. In addition, the second data DATA2 after the operation is transmitted to the processor GPP before passing through the mailbox of the _120, the mechanism is: the coprocessor CP needs to send a request to the mailbox 120 to send the second data DATA2 Write to mailbox 120. Next, the mailbox 12〇 issues an interrupt command to the general-purpose processor GPP' after the second data DATA2 is written, so that the general-purpose processor GPP reads the second data data2. Please refer to FIG. 3. FIG. 3 is another embodiment of an asymmetric dual-core asymmetric transmission system employing the diagram. In this embodiment, the general purpose processor Gpp is connected to the (four) first data DATA1 from an external camera 132 (which may also be a camera). The first data DATA1 here is an image picture (or image material). The fresh calculus processing of the cooperative processing HCT is a partial pattern in the silk detection image, for example, detecting the "cross image 12 201211771" in the image.

Vvv_, *- 010 35295twf.doc/type I. The coprocessor CP will detect the "cross pattern, the location is very good... it is passed back to the general processor (10) 'where the coordinate value ^) P For the second data DATA2. From this f paste point of view, the data amount of the _data Datai ^ picture 'co-processor cp performs the detection algorithm, • -WDATA2 is the position coordinate value (x, y), the second data Data2 passes the mechanism of the post & 120 And back to the general purpose processor Gpp. The mailbox 120 issues an interrupt command to the general-purpose processor Gpp, and the general-purpose φ towel service program receives the interrupt command. Then, the general-purpose processor GPP: uses the program to receive the "cross-pattern, the position coordinate value (x, y) ^ although the above Several possible types have been described in the embodiments for asymmetric transmission systems, but those of ordinary skill in the art will appreciate that the application of the present invention is not limited to the above-described possible types. In other words, as long as 1 or the architecture of the asymmetric dual-core asymmetric transmission system of FIG. 3 is in line with the spirit of the present invention. Several embodiments are hereinafter described so that those skilled in the art can further understand the spirit of the present invention. And the invention is implemented. Please refer to FIG. 3. Referring again to FIG. 3, in an embodiment, if the transmitted first data DATA1 is a continuous plane, and the second data Data2 to be returned is adjacent in the continuous plane. The difference between the two sides, the detection algorithm executed by the coprocessor cp can be designed to analyze and compare the adjacent two faces in the continuous face. One embodiment, the transmission system 100 is symmetric if not done voice compression for voice f material calculated, this system can be designed to: (. Capturing device such as a microphone or speech) general purpose processor GPP receives camera 13213201211771

—.**0 35295twf.doc/I The voice data transmitted is used as the first data DATA1, and the general processor Gpp transmits the first data DATA1. The mathematical operation of the cooperative processor CP is to perform voice compression calculation for the voice data. The returned second data DATA2 is the compressed voice data. In another embodiment, when the transmitted first data DATA1 is a file and the second data DATA2 to be returned is a compressed file, the mathematical operation of the coprocessor CP can be designed to compress the data for the file.

The J J J 僻 仅 仅 仅 仅 仅 仅 仅 仅 僻 僻 僻 僻 僻 僻 僻 僻 僻 僻 僻 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 This lie can also be changed according to the demand (four) recording device _. Therefore, this application is not used; it is made in several possible types. Hybrid Figure 4 is a flow diagram of a heterogeneous dual core < method in accordance with an embodiment of the present invention. This asymmetric transmission method 400 is applicable to the step-by-step transmission system. This asymmetric transmission method 400 includes 1

Enjoy memory '; then S41: Suddenly write the first data to the memory to read the -L in =:3: the data is processed mathematically to get ^ 0 to the first - sulfur due to cry In the case of step S440, the second information is written to the mailbox, and the data flow is much smaller than the data of the first---the data is transmitted. After being transmitted to the general-purpose processor, in the process of exhausting, the surface transmission system and method of the embodiment of the present invention can be 14 201211771

v^ w010 35295twf.doc/I to solve the technical problem of wasting memory resources and excessive hardware interruption in the prior art, and can provide more efficient data transmission, at least has the following characteristics: (1) general-purpose processor transfer The amount of data for the coprocessor is large, the amount of data transmitted by the coprocessor to the general processor is small, and the shared memory is used for data transmission without two-way communication; (2) the shared memory does not use the interrupt mechanism; The coprocessor only has the math algorithm to do the arithmetic. After the coprocessor executes the algorithm, the flag register can be checked to confirm whether the shared memory allows it to read the data, so there is no need to use the interrupt mechanism to remind the coprocessor to read the data, which can save the use of the interrupt. And (4) use the mailbox mechanism, without pre-planning the space of shared memory 'can save memory resources. The present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of protection of this invention is subject to the definition of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of an asymmetric dual core asymmetric transmission system in accordance with an embodiment of the present invention. 2 is a schematic diagram of shared memory in accordance with an embodiment of the present invention. - Figure 3 is a consistent example of the use of the heterogeneous dual core asymmetric transmission system of Figure 1. Figure 4 is an asymmetric dual-core asymmetric transfer wheel in accordance with an embodiment of the present invention.

35295twf.doc/I 201211771 W W V 1 IV %/▲ Flow chart of the method. [Main component symbol description] 1〇〇: heterogeneous dual core asymmetric transmission system 110: shared memory 120: mailbox 132: camera CP: coprocessor DATA1: first data DATA2: second data FR: flag temporary storage GPP: General Purpose Processor 400: Heterogeneous Dual Core Asymmetric Transmission Method S410~S450: Steps

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Claims (1)

201211771 VVV—*· * V -010 35295twf.doc/I VII. Application for patents: heterogeneous dual core non-pair _ lose _ a shared memory; i bracket. First, use the processor, lightly connect the share one The first data is written to the shared memory; 4 using a processor to couple a coprocessor, coupled to the ping = different from the general processor, the synergy ": the second data of the second processor and the first It is concluded that the flow f is small, the data flow of the first data; and the data box of the data is lightly connected to the ft between the general processing 11 and the reliance processor transmitted by the coordinator. The mailbox is sent to the processing first to write to the pass ==== asymmetry of the mouth = universal place, the first data writes the opposite direction and the processor reads the first data from the shared memory. In the opposite direction, the same amount of data as the first data will be transmitted from the coprocessor to the first capital, and the same information will be the same as the fly-neck. (4) The amount of material. The asymmetry of the heterogeneous dual core described in item 1 of the patent application scope is only by] The data flow direction of the second data is a single direction, and the coprocessor writes the second data to the mailbox, and the pass 17 201211771 ----------0 35295twf.d〇c /I box! Take the second data 'cannot be reversed from the mailbox: the information on the second data is sent back to the coprocessor and the helmet is from the same data as the second data. The data is written to the size of the i, and the data referred to is equivalent or similar to the data of the second data / J, 0 4 · The heterogeneous dual core asymmetry as described in the patent (4) The system 'the towel shared mark includes: flag temporary storage [the flag: the flag content of the register is used to record the write authority, the read permission, the write start position of the memory and the read memory The termination position is as follows: I. The heterogeneous dual-core asymmetric 1 transmission system described in claim 4 of the patent application, the processing of the towel and the co-processing H to poll the flag "temporary (four) square wire to share the 贱Remembering that the processor performs a write operation according to the flag content of the flag register, the coprocessor According to flag the content of the flag register to do the reading operation. 6. The asymmetry of the heterogeneous dual core according to claim 1, wherein the first data is a face, and the operation of the coprocessor is to position the partial pattern in the facet. The second data is detected as the exact location of the partial pattern in the face. 7. The heterogeneous dual-core asymmetric transfer system of claim 1, wherein the first data is a continuous face, and the operation of the coprocessor is for two adjacent ones of the continuous faces. The picture is compared and analyzed, and the first data is the difference point of the adjacent facets in the continuous facet. 8. The heterogeneous dual-core asymmetric transmission system according to claim 1, wherein the first data is a voice data, and the coprocessor υ1° 35295twf.doc/I 201211771 'The second information is 9 if the application for the full-time division of the second item of the heterogeneous double such as 'the first-data is - file' the coprocessor's = m financial data compression, the second information is Wei of_. 10. The tea system of claim i, wherein the coprocessor sends to the mailbox: please:::;:: at:; write: the mailbox, and then the mailbox issues an interrupt command to the Passing the processor to cause the general purpose processor to read the second data. The asymmetric transmission method is applicable to the non-symmetric transmission method: 'The asymmetric transmission system includes a general-purpose processor, a co-co-processor, and a mailbox, and the coprocessor is similar to The universal device &quot; 'the asymmetric transmission method includes: using a processor to write the first data to the shared memory; U processing the same data from the shared memory; The first data is processed to obtain a first material; the collaborative processing n writes the second data to the mailbox, wherein the data flow of the first resource is smaller than the data flow of the first data; The mailbox transmits the second data to the general purpose processor.僧!!·如如(四)Specialty (4) 11 items of heterogeneous dual-core non-orientation method · 'where the data flow direction of the first data is a single party, the general processor writes the first data to The shared memory is read by the coprocessor from the shared memory, 19 201211771 —, —* 0 35295twf.doc/I cannot be _ from the shared memory in the opposite direction — The data of the data transfer device J' cannot write the same amount of data from the coprocessor to the shared memory, wherein the same amount of information is equivalent to or similar to the data of the first data. Quantity. The nominal value of the 11th item of the patented surface is the non-pair of '', and the direction of the data flow for transmitting the second data is single: the second data is written by the coprocessor only The mail = 'and the general processor reads the second reliance from the mailbox, and the benefit method will return the same amount of data of the second data to the second s. The same amount of information referred to in the same amount of information in the second box of information is equivalent or similar to the size of the data. It is said that the heterogeneous dual core described in item 11 of the scope of interest is not right, and the shared memory includes a flag register, which is used to record the write permission and read. Take the permission, write the start position of the hidden body and the end position of the read memory. </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The = device performs a write operation according to the content 'the collaborative processing code palm flag saves the flag content to do the reading action.偻 · = · If the application of patent scope 帛 11 of the heterogeneous dual core non-computation operation 方法 1 method = 'where the first data is a picture, the coprocessor's 疋 for the local pattern in the picture Position detection, the second data 20 201211771 xw-010 35295twf.doc/I is the exact location of the partial pattern in the picture. 17. The heterogeneous dual core method according to claim 5, wherein the first data is a continuous surface, and the synergistic processing operation is performed for adjacent two sides of the continuous surface. For analysis and comparison, the data is the difference point between two adjacent faces in the continuous facet. It is said that the heterogeneous dual-core non-oblique device described in item 11 of the scope of interest is a speech data. The collaborative processing is a speech compression calculation for compressed audio data. The first bell is a file, the case of the coprocessor.疋.+Checking the file, the second information is the secret of the secret. The heterogeneous dual core described in item 11 is not sent to the mailbox by the second data core coprocessor. After processing the r mailbox, the mailbox then issues an interrupt command to the general title thief to enable the listener to read the second 4 21