201225215 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種製作溝渠式功率半導體元件的方法，尤指一 種製作具有低閘極電容之溝渠式功率半導體元件的方法。 【先前技術】 功率金氧半場效電晶體(Power Metal Oxide Semiconductor Field201225215 VI. Description of the Invention: [Technical Field] The present invention relates to a method of fabricating a trench type power semiconductor device, and more particularly to a method of fabricating a trench type power semiconductor device having a low gate capacitance. [Prior Art] Power Metal Oxide Semiconductor Field (Power Metal Oxide Semiconductor Field)
Effect Transistor，簡稱power MOSFET)是一種可以廣泛使用在類比 電路與數位電路的場效電晶體，由於具有低導通電阻及高切換速度 的優點’功率金氧半場效電晶體已成為高頻低壓功率元件的主流。 目前常見制於f耻敵、電祕應n、汽車電打n统、電 池系統、魏安定減軌設備上，主要的魏為功轉換⑻ Conversion) ^ (Switch) > 護(Protection)以及整流(Rectify)等。 201225215 十於習知的溝渠式功率金氧半場效電晶體之結構甲，當需提高元 ^度以_、元件面_及提升單位面積可提供之電流時，問極溝 渠的寬度必須隨之縮小’造成間極與沒極之間的電容量(Cgd)變大， =極的歧電速㈣慢㈣彡響元件的魏。餅低溝渠式功率金 的=晶體?問極與沒極之間的電容量，可藉由增加溝渠底部 =〃、層的厚絲達成。然*，於習知的溝渠式 ，_部鳴靖細時也會使^ 而無去二4溝渠式功率金氧半場效電晶體元件的起始賴升高，因 無法同時兼顧低起料壓與高頻率操作的需求。 【發明内容】 本七明之目的之—在於提供—種製作溝渠式 方法，可解決習知技術無法兼顧低起始電壓與高頻率操作==的 方法為=二本發明提供一種製作溝渠式功率半導體元件之 上述方法包括下列步驟：首先 之 :刻方式於該半導體基底中形成複數個溝渠：：接:’ 顧製程，以於該等溝渠之該等側壁植入至少—離子厂離子 陶製程，對該等溝渠之該等底部 秋後= =的该介電層厚度大於各該溝渠之 ^之讀 201225215 式功率半導體元件之閘極電極。 本發明利用於溝渠内進行離子佈植製程後，對溝渠底部進 =降低_之底部及賴之底部與_交界處麵子植入影響所 :的雜不均勻現象，使得後續閘極介電層生長時能維;良 電六因時增加溝渠底部之_介電層厚度以降低閘極 電令。因此本發明之低閘極電容溝渠式功率半導體元件可用於 式功率金氧半場效電晶體並兼顧低起始電壓與高頻率操作的需求Γ 【實施方式】 請參考第1圖至第9圖。第1圖 溝渠式功率轉觀件之方料f第9圖繪不了本發明的製作 !圖所-坦 實施例的示意圖。首先如第 -不’提供-料體基底1G，在本實施例中，半導體美底1〇 導體材質所構成之單層或複合層的半導體紐^例如 土底10可包括-η型摻雜之半導體晶圓1〇1，以及一蟲日居 =，==輕摻嶋層，但概為限。接_丨 牵化石表面形成一圖案化硬遮罩層11，隨後再利用圖 案匕更遮罩層U當作#刻硬遮罩來對半導體基底ig進行一触刻製 ::渠:。非等向性罐程，以在半導體基底1〇 _形成複數個 ^如第2騎示，進行—離子佈植製程13，以於半導體基底 内之各溝渠12 _壁分別植入至少—讎子。在本實施例中， 201225215 此離子佈植製程13係以降低各溝渠12的底部及各溝渠12的底部與 側壁交界處觀人離子的程度及可紐為前提所加以·者，例如 其可為一斜向(tilt)離子佈植製程，但不以此為限。而且，此離子佈 植製程13所植入之離子可為氮離子等不影響元件電性的離子類 型’但本發明亦不以此為限。接續可依產品需求或依元件特性考量 另選擇性進行—離子佈植餘，用來植人導電摻質以機此溝渠式 功率半導體元件的間值電壓_沾〇1(1她哪，雜）。啊在本實 ·,例中，’冓渠的深寬比、圖案化硬遮罩層u的厚度與斜向離子佈植 製私的角度均亦為重要製_整參數，較佳者不讓各溝渠12的底部 及各溝渠12的底部無敍界處抛人軒，此外，时形成溝渠 12的圖案化硬鮮層u並不在溝渠12形成之後直接被移除，圖案 化硬遮罩層11還被_於後續離子佈植製程及後續進行其他敍刻 製程時對半導體基底1〇的表面形成保護作用，以降低半導體基底 1〇的表面被植入離子的程度及可能性。 土 _ _ 如第3圖所示，在離子佈植製程13之後，於半導體基底1〇上 全面形成-保護層14。在本實施例中，保護層14係利用—化 相沉積(CVD)製程所形成，但本發明並不以此為限。 如第4圖所示，在保護層14形成後，隨即進行—敍刻製 除各溝渠12内之底部的保護層14，以於各溝渠12的側壁分別 -側壁子(spacer's。在本實施例中，該触刻製程可 乾蚀刻製程。 ㉟非·#向性 201225215 溝渠子後’如第5騎示’本1找實_會再對 之底。P進仃一溝渠底部侧製程，用以移除 體基底10，進而確保各溝渠12之底部的半導 =離子佈植製㈣所植人_子，以避=广= ，渠底部崎㈣，侧壁子戰同時兼具扮演f=丁 之側壁的角辛，，、；士^ + 只昨邊/冓渠12 的離子植人效果不受^渠12之侧壁被離子佈植製程13形成 如第6圖卿，_鹪底部侧縣 =程，側壁子⑽及圖案化硬遮罩層η-/移:： ^中’ _離_製程可為—等向性刻製程，但本 以此為限。同時該__製程對側壁子14 與半導體縣川具有—相概，用崎 程對溝渠12，鶴的料縣底丨㈣ $ 12之侧壁被料崎郎糊料⑽Γ 如第7 _示，之後於溝渠12表面形成—介電層15，其中， ^成^渠12之側壁的介電層15係用做本發明之溝渠式功率半導 八疋件的閘極介電層(GateInsul迦），而且形成於溝渠12之底 ”電層I5厚度大於形成在溝渠u之側壁的介錢1S厚度。在本實 201225215 :中’形成介電層15之步驟較佳係利用一熱氧化製程 為乳峨’但亦不以此為限。此外，值得注意的二 ^之㈣㈣子舰製程13形成的離子植人效果於^^ 刻製程時被側壁子14S所保護，故於形成介電層15時， 側壁會受到先前離子佈植製程13植入之氮離在之 該熱氧化製程時，介電；^ 15於、、^ u 等w成在進行 之側壁上的氧化生成速率相 1S H 底相介電層15的氧化生成速率，而形成介電居 於溝渠12底部厚度較厚的情況。換句話說 " =12之側壁佈植氮離子的方法來增加溝渠…部的介= 的厚度，且同時維持溝渠12之側壁的介電層厚度 層5 Γ可有效達到降低嶋辦導體元件之輯容且:1 其閾值電壓(Vth)的目的。 曰力 如第8圖所示，在形成介電層15之後，於溝渠12内填入一導 電材料，其中鱗電材料係料該溝渠式功率半物元件之問極電 極16。在本實施射，該導電材料係、由-半導體材料，例如多晶 石夕，並藉由-同步(,·_)摻雜方式或離子佈植等方式形成一摻雜半 導體層’然後再藉由-黃絲刻製程(ph〇t〇_EtchmgPr〇cess)將溝渠 12以外之該導電㈣去除，但本發明不以此為限。 如習知該項技藝者與通常知識者所熟知，在形成間極電極16 之後，接著如第9圖所示’於半_基底1G中形成至少-基體摻雜 區_州7，並於基體摻_ 17内形成至少一源極區18。然後於半 201225215 導體基底ίο上方全面形成一層間介電層19，覆蓋閉極電極16、基 體摻雜區17與源極區18。隨後選擇性姑刻部份之層間介電層19直 至源祕18 ’以於層間介電層19中侧出所需之接觸插塞洞2〇， 然後再進行-離子佈植製程’經由各綱插塞洞2G驗基體推雜區 π内形成-重摻雜區21並電連接源極區18。接著於各接觸插塞洞 20,形成導電層’例如先形成包含鈦、氮化鈦等之阻障層，再沉積 嫣等之主導電層，然後再進行化學機械研磨(CMp)等之平坦化 (PWiza㈣製程’以於層間介電層19中形成一源極接觸插塞22 實質接觸重摻籠21。最後於制介電層19上形成—源極金屬層 23 ’且源極接糖塞22電連接重摻顏21與源極金屬層a，至此 完成溝渠式功率轉體元件4〇的製程。此外，本較佳實施例亦可在 形成接觸插塞洞20之後’直接於層間介電層19上以及接觸插塞洞 中形成導電金屬層’以同時形成源極金屬層a與源極接觸插 =。在本實施例中，基體摻雜區17係為1型基體，源極㈣ 摻雜重摻雜19係為p+型區，而源極接觸插塞2^係為 鶴’但本發明並不以此為限。 側壁^於溝_進行料佈植抛後，搭配一 V纽對賴麵進行侧，降低賴 =:壁交界處受離子植入影響所造成的離子推雜不均勻現;= =極靖生長時能維持良好的輪廊形狀，且同時增二 2底。卩之介電層的厚度以降低閘極電容1此，本發明僅對 側壁佈植氮離子的方法所製備之溝渠式功率半導體元件，不 201225215 U低馳電容’·啊兼顧侧值電顯高頻率操作的需 =可咖鳴咖胸睛級_可靠度不Effect Transistor (power MOSFET) is a kind of field effect transistor that can be widely used in analog circuits and digital circuits. Due to its low on-resistance and high switching speed, 'power MOS half-effect transistor has become a high-frequency low-voltage power device. Mainstream. Currently common in f shame, electric secret should n, car electric n system, battery system, Wei Anding derailment equipment, the main Wei Weigong conversion (8) Conversion) ^ (Switch) > Protection and rectification (Rectify )Wait. 201225215 Ten is a well-known structure of a trench-type power MOS field-effect transistor. When it is necessary to increase the current by _, the component surface _ and the current supplied by the unit area, the width of the pole trench must be reduced. 'Causes the capacitance between the pole and the pole (Cgd) to become larger, = the speed of the pole of the pole (four) is slow (four) the Wei of the component. Piece low ditch power gold = crystal? The capacitance between the pole and the pole can be achieved by increasing the bottom of the trench = 〃, the thick layer of the layer. However, in the well-known ditch type, the _ part of the Jingjing fine will also make ^ and the second 4 ditch type power MOS half-effect transistor components rise, because it can not take into account the low material pressure The need for high frequency operation. SUMMARY OF THE INVENTION The purpose of the present invention is to provide a method for making a trench, which can solve the problem that the conventional technology cannot balance the low initial voltage and high frequency operation == = 2. The present invention provides a trench type power semiconductor. The above method of the component comprises the following steps: firstly: forming a plurality of trenches in the semiconductor substrate by: engraving: a process to implant at least the ion plant ion ceramic process on the sidewalls of the trenches, The thickness of the dielectric layer at the bottom of the trenches after the fall = = is greater than the gate electrode of the 201225215 type power semiconductor device of each of the trenches. The invention utilizes the heterogeneous phenomenon of the bottom of the trench to reduce the bottom of the trench and the surface of the trench and the surface of the trench to be implanted in the trench, so that the subsequent gate dielectric layer is grown. Time energy dimension; good electricity six times increase the thickness of the dielectric layer at the bottom of the trench to reduce the gate electrical order. Therefore, the low gate capacitance trench type power semiconductor device of the present invention can be used for a power MOSFET and a low initial voltage and high frequency operation. [Embodiment] Please refer to Figs. 1 to 9. Fig. 1 is a schematic diagram of the embodiment of the ditch type power transfer device. Figure 9 is a schematic view of the embodiment of the present invention. First, as the first-negative-material substrate 1G, in the present embodiment, the semiconductor layer of the single-layer or composite layer composed of the semiconductor material of the semiconductor substrate, for example, the soil substrate 10 may include -n-type doping. The semiconductor wafer 1〇1, as well as a worm day ==== light erbium layer, but it is limited. Then, a patterned hard mask layer 11 is formed on the surface of the fossil, and then the pattern U The non-isotropic tank process is performed to form a plurality of cathodes on the semiconductor substrate, such as the second riding, to perform an ion implantation process 13 for implanting at least the germanium in each of the trenches 12 _ walls in the semiconductor substrate. . In the present embodiment, 201225215, the ion implantation process 13 is provided on the premise that the bottom of each trench 12 and the bottom of each trench 12 are viewed at the boundary between the bottom and the sidewall, and may be A tilt ion implantation process, but not limited to this. Moreover, the ions implanted in the ion implantation process 13 may be ion types such as nitrogen ions that do not affect the electrical properties of the device, but the invention is not limited thereto. The connection can be selectively carried out according to the product requirements or depending on the characteristics of the components. The ion cloth is used for implanting the conductive dopant to calculate the voltage value of the trench-type power semiconductor device _ 〇 〇 1 (1 she, miscellaneous) . In this case, in the example, the aspect ratio of the channel, the thickness of the patterned hard mask layer u, and the angle of the oblique ion cloth are also important parameters, preferably not allowed. The bottom of each trench 12 and the bottom of each trench 12 are not delineated, and the patterned hard layer u forming the trench 12 is not directly removed after the trench 12 is formed, and the hard mask layer 11 is patterned. The surface of the semiconductor substrate 1 is also protected by a subsequent ion implantation process and subsequent subsequent etching processes to reduce the extent and possibility of implanting ions on the surface of the semiconductor substrate. Soil _ _ As shown in Fig. 3, after the ion implantation process 13, a protective layer 14 is entirely formed on the semiconductor substrate 1A. In the present embodiment, the protective layer 14 is formed by a chemical vapor deposition (CVD) process, but the invention is not limited thereto. As shown in FIG. 4, after the protective layer 14 is formed, the protective layer 14 at the bottom of each trench 12 is sequentially formed to form a spacer for each side wall of the trench 12. In this embodiment, In the process of the engraving process, the etching process can be dry. 35 non-# directional 201225215 After the ditch, the 'female 5th ride' is the first one to find the real _ will be the bottom. P into the bottom side of the ditch, for the process The body substrate 10 is removed, thereby ensuring that the bottom of each trench 12 is semi-conducted = ion implanted (four) implanted _ sub, to avoid = wide =, the bottom of the canal (four), the side wall warfare simultaneously plays the role of f = D The corner of the side wall, Xin,,; Shi + + only the ion implant effect of the yesterday / the channel 12 is not affected by the side wall of the channel 12 is formed by the ion implantation process 13 as shown in Figure 6 = path, sidewall spacer (10) and patterned hard mask layer η-/shift:: ^中' _ _ _ process can be - isotropic engraving process, but this is limited to this. At the same time the __ process to the side wall 14 It has a similarity with the semiconductor county, and it is the surface of the ditches 12, which is the surface of the ditches 12, which is the surface of the ditches. a dielectric layer 15 in which the dielectric layer 15 of the sidewall of the trench 12 is used as the gate dielectric layer (Gate Insul) of the trench type power semiconductor octagonal device of the present invention, and is formed in the trench The thickness of the electric layer I5 is greater than the thickness of the dielectric layer 1S formed on the sidewall of the trench u. In the present 201225215: the step of forming the dielectric layer 15 is preferably a thermal oxidation process for the chyle 'but not In addition, it is worth noting that the ion implantation effect formed by the (4) (4) sub-ship process 13 is protected by the sidewall 14S during the etching process, so when the dielectric layer 15 is formed, the sidewall is subjected to the previous The ion implantation process 13 is implanted with nitrogen in the thermal oxidation process, dielectric; ^ 15 、, ^ u, etc., oxidized to form a rate phase on the sidewall of the 1S H bottom dielectric layer 15 The rate of oxidation is formed, and the formation of dielectric is thicker at the bottom of the trench 12. In other words, the method of implanting nitrogen ions on the sidewall of the "=12 increases the thickness of the trenches while maintaining the trenches 12 The dielectric layer thickness layer 5 侧壁 of the sidewall can effectively reduce the series of conductor elements容容: 1 The purpose of its threshold voltage (Vth). As shown in Fig. 8, after forming the dielectric layer 15, a conductive material is filled in the trench 12, wherein the squama electrical material is the trench power. The electrode electrode 16 of the semiconductor element. In the present embodiment, the conductive material is formed by a semiconductor material such as polycrystalline stone and by a - synchronous (, _) doping method or ion implantation. A doped semiconductor layer ' is then removed by the - yellow wire engraving process (ph〇t〇_EtchmgPr〇cess) except for the conductive (four) of the trench 12, but the invention is not limited thereto. As is well known to those skilled in the art, after forming the interpole electrode 16, then as shown in Fig. 9, 'at least the base doped region_State 7 is formed in the half-substrate 1G, and is on the substrate. At least one source region 18 is formed within the doped -17. Then, an interlayer dielectric layer 19 is formed over the semiconductor substrate ίο at half 201225215, covering the closed electrode 16, the substrate doping region 17, and the source region 18. Then, the interlayer dielectric layer 19 is selectively engraved to the source 18' to form the desired contact plug hole 2 in the interlayer dielectric layer 19, and then the ion implantation process is performed. The plug hole 2G forms a heavily doped region 21 in the base dummy region π and is electrically connected to the source region 18. Then, a conductive layer is formed on each of the contact plug holes 20, for example, a barrier layer containing titanium, titanium nitride, or the like is formed, and a main conductive layer such as tantalum is deposited, and then planarization by chemical mechanical polishing (CMp) or the like is performed. (PWiza (four) process 'to form a source contact plug 22 in the interlayer dielectric layer 19 to substantially contact the heavily doped cage 21. Finally, a source metal layer 23' is formed on the dielectric layer 19 and the source is connected to the sugar plug 22 The method of electrically connecting the surface 21 and the source metal layer a is completed, and the process of the trench power conversion element 4 is completed. Further, the preferred embodiment can also be directly formed on the interlayer dielectric layer after forming the contact plug hole 20. A conductive metal layer is formed on the 19 and the contact plug hole to simultaneously form the source metal layer a and the source contact plug =. In this embodiment, the base doped region 17 is a type 1 substrate, and the source (four) is doped. The heavily doped 19 series is a p+ type region, and the source contact plug 2^ is a crane', but the invention is not limited thereto. The side wall ^ in the trench _ after the material is planted and thrown, with a V New Zealand Side of the face, reduce the lag =: the ionization unevenness caused by the ion implantation at the wall junction; = = pole When growing, it can maintain a good shape of the corridor, and at the same time increase the thickness of the dielectric layer to reduce the gate capacitance. Therefore, the trench type power semiconductor prepared by the method of implanting only nitrogen ions in the sidewall of the present invention. Components, not 201225215 U low-capacitance capacitors '· ah take into account the side value of the electric high frequency operation needs = can be singular coffee chest level _ reliability is not
【圖式簡單說明】 第1圖至第9圖繪示了本發明的製作溝渠式功率半導體_ 的一較佳實施例的示意圖。 /ir 【主要元件符號說明】 10 半導體基底 1Q2磊晶層 12 溝渠 14 保護層 15 介電層 17 基體摻雜區 19 層間介電層 21 重摻雜區 23 源極金屬層 101半導體晶圓 11 圖案化硬遮罩層 13 離子佈植製程 14S側壁子 16閘極電極 18 源極區 20 接觸插塞洞 22 源極接觸插塞 40溝渠式功率半導體元件BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 through 9 are schematic views showing a preferred embodiment of the trench type power semiconductor of the present invention. /ir [Major component symbol description] 10 Semiconductor substrate 1Q2 epitaxial layer 12 trench 14 protective layer 15 dielectric layer 17 substrate doped region 19 interlayer dielectric layer 21 heavily doped region 23 source metal layer 101 semiconductor wafer 11 pattern Hard mask layer 13 ion implantation process 14S sidewall spacer 16 gate electrode 18 source region 20 contact plug hole 22 source contact plug 40 trench type power semiconductor device