TW201905975A - Method of fabricating semiconductor device - Google Patents

Abstract

A method of fabricating a semiconductor device includes the following steps. First, form a gate structure on a semiconductor substrate. Then, use a mask having two transparent regions through a photolithography process to form a photoresist layer having two openings in the semiconductor substrate. A first photoresist layer of the photoresist layer between the two openings is aligned to the gate structure and formed on the gate structure. The width of the first photoresist layer is smaller than that of the gate structure such that a first side portion and a second side portion of the gate structure are not covered by the first photoresist layer. Next, carry out ion implantation to form lightly doped drain regions in the semiconductor substrate which are not covered by the photoresist layer.

Description

 Semiconductor device manufacturing method  

The present invention relates to semiconductor devices, and more particularly to a method of fabricating a lightly doped drain semiconductor device.

In order to increase the density of components and improve the speed and performance of the operation, the size of the components is continuously reduced in the manufacturing process of the semiconductor device. Taking a MOS transistor as an example, the vertical electric field and the horizontal electric field are increased due to the shortening of the channel length and the decrease in the thickness of the gate oxide layer. As a result of the increase in the horizontal electric field, the velocity of the carriers in the channel is accelerated. When these carriers are accelerated in the channel to obtain sufficient energy, the probability of these carriers being injected into the gate oxide layer is increased, or the oxide layer is formed. The gate current, or the carrier, will create an electron hole pair at the 汲 extreme. Therefore, when the channel of the MOS transistor is shortened, the number of carriers whose channel is close to the drain will rise to cause a hot electron effect. In the hot electron effect, part of the electrons are injected into the gate oxide layer, and the corresponding holes are generated to flow to the substrate to generate the substrate current. The other part of the hole is collected by the source, which strengthens the phenomenon of the NPN bipolar transistor, which causes more carriers to multiply, and may even cause an electrical breakdown.

For the foregoing problems, the prior art has proposed a Lightly Doped Drain (LDD) to mitigate or avoid damage to the semiconductor device caused by the thermoelectric effect. In the semiconductor process, the conventional light-doped bungee manufacturing method can still be further improved; and the intention of the present invention is to propose a new semiconductor device manufacturing method for the lightly doped gate.

According to a technical feature of the present invention, a method of fabricating a semiconductor device according to the present invention includes at least the following steps. First, a gate structure is formed on a semiconductor substrate. Then, a photoresist layer is formed on the gate structure, the photoresist layer has at least a narrow portion, and the width of the narrow portion is smaller than the width of the gate, such that a first side portion and a second portion of the gate electrode The side portions are exposed on both sides of the photoresist layer. Ion implantation is then performed to form a lightly doped drain region in the semiconductor substrate on either side of the gate structure.

The first side portion and the second side portion respectively exposed on both sides of the photoresist layer have substantially equal widths B. Further, the narrow portion of the photoresist layer has a width S, the gate structure has a width L, and the respective widths L, B, and S respectively conform to the specifications of the process capability. Further, the energy used for the ion implantation is 100 keV to 200 keV.

According to another technical feature of the present invention, a method of fabricating a semiconductor device according to the present invention includes at least the following steps. First, a gate structure is formed on a semiconductor substrate. And using a mask defined by two light-transmissive regions, forming a photoresist layer having two openings on the semiconductor substrate by a lithography process; wherein the photoresist layer is located between the two openings A first photoresist layer is formed on the gate structure in alignment with the gate structure, and a width of the first photoresist layer is smaller than a width of the gate structure, such that a first side of the gate structure And a second side portion is exposed on both sides of the first photoresist layer. Next, ion implantation is performed to form a lightly doped drain region in the semiconductor substrate exposed on both sides of the gate structure of the photoresist layer.

The first side portion and the second side portion respectively exposed on both sides of the first photoresist layer have substantially equal widths B. In addition, the width of the first photoresist layer is S, the width of the gate structure is L, and L, B, and S respectively meet the specifications of the process capability. Further, the energy used for the ion implantation is 100 keV to 200 keV.

The present invention will now be described in detail by way of example embodiments with reference to the accompanying drawings.

10‧‧‧Semiconductor substrate

12‧‧‧ gate structure

12a‧‧‧ gate oxide layer

12b‧‧‧ gate

14‧‧‧ photoresist layer

16‧‧‧Lightly doped bungee zone

18‧‧‧Ion implantation

20‧‧‧Open area

31-34‧‧‧MOS transistor characteristic curve

40‧‧‧Semiconductor substrate

42‧‧‧ gate structure

42a‧‧‧ gate oxide layer

42b‧‧‧ gate

44‧‧‧ photoresist layer

44a‧‧‧First photoresist layer

46‧‧‧Lightly doped bungee zone

48‧‧‧Ion implantation

OP1-OP2‧‧‧ openings

61-63‧‧‧MOS transistor characteristic curve

71-72‧‧‧MOS transistor characteristic curve

81-82‧‧‧MOS transistor characteristic curve

L‧‧‧ width of gate structure

S‧‧‧The width of the first photoresist layer

B‧‧‧Width of the first (second) side

SP1‧‧‧ first side

SP2‧‧‧ second side

Figures 1A to 1C show the manufacturing process of a conventional lightly doped drain.

Fig. 2 is a view showing a corresponding layout of Fig. 1B.

Figs. 3A to 3B are diagrams showing electrical characteristics of the MOS transistor obtained in the layout of Fig. 2.

4A-4C show a manufacturing process of a lightly doped drain according to an embodiment of the present invention.

Fig. 5 shows a layout corresponding to Fig. 4B.

Fig. 6 is a graph showing the characteristics of the substrate current Isub of the MOS transistor with respect to the gate voltage Vgate.

Fig. 7 is a graph showing the characteristic of the drain current Idrain of the MOS transistor with respect to the gate voltage Vdrain.

Fig. 8 is a graph showing the breakdown voltage characteristics of the MOS transistor.

The following description is of various embodiments and aspects of the invention. The intent is to exemplify the general principles of the invention and should not be construed as limiting the scope of the invention, which is defined by the scope of the claims.

Figures 1A to 1C show the manufacturing process of a conventional Lightly doped Drain (LDD). In FIG. 1A, a gate structure 12 is formed on a semiconductor substrate 10, such as doped-silicon, which includes a gate oxide layer 12a and, for example, The doped-poly gate 12b is doped, but is not limited thereto. In Fig. 1B, a photomask layer 14 is formed on the semiconductor substrate 10 by a photomask (not shown) in cooperation with a lithography process. Fig. 2 is a view showing a corresponding layout of Fig. 1B. As can be seen from Figures 1B and 2, the photomask (not shown) used has a light transmissive region defining an open region 20 (Fig. 2) of the photoresist layer 14. Next, ion implantation 18 is performed to form lightly doped drain regions 16, which are shown in FIG. 1C after removal of the photoresist layer 14.

In the above-described conventional method of manufacturing a lightly doped gate, most of the gate structure 12 is exposed in the open region 20 of the photoresist layer 14, so that high energy ions are easily used in high energy ion implantation. Penetration from the gate structure 12 to the semiconductor substrate 10 results in drain to source punch-through leakage. In addition, taking the layout structure shown in Fig. 2 as an example, the thermoelectric effect is still very serious in medium voltage (5V~8V) applications. In order to further reduce the thermoelectric effect, the width of the gate structure 12 is generally increased (and the channel length of the MOS transistor is correspondingly increased) to reduce the lateral electric field in the case of a high drain voltage. In Fig. 3A, a curve 31 indicates characteristics of a MOS transistor having a gate width L of 0.8 μm, and a curve 32 indicates characteristics of a MOS transistor having a gate width L of 0.85 μm. As shown in FIG. 3A, as the width L of the gate structure 12 increases, the substrate current Isub decreases. However, as the width L of the gate structure 12 increases, the size of the semiconductor device and its current driving capability are affected. In Fig. 3B, curve 33 represents the characteristics of the MOS transistor having a gate width L of 0.8 μm, and curve 34 represents the characteristics of the MOS transistor having a gate width L of 0.85 μm; as shown in Fig. 3B, with the gate As the width L of the pole structure 12 increases, the drain current Idrain also decreases.

4A-4C show a manufacturing process of a lightly doped drain according to an embodiment of the present invention. Fig. 5 shows a layout corresponding to Fig. 4B.

In FIG. 4A, a gate structure 42 is formed on a semiconductor substrate 40, such as a doped-silicon substrate, the gate structure 42 includes a gate oxide layer 42a and For example, the doped polysilicon gate 42b is doped, but is not limited thereto.

In FIG. 4B, a mask (not shown) defining two light-transmissive regions is used to form a photoresist layer 44 having two openings OP1, OP2 (Fig. 5) in the lithography process. On the substrate 40. The first photoresist layer 44a of the photoresist layer 42 between the two openings OP1 and OP2 is aligned with the gate structure 42 and the width S of the first photoresist layer 44a is smaller than the gate. The width L of the structure 42 is such that a first side portion SP1 and a second side portion SP2 of the gate structure 42 are exposed on both sides of the first photoresist layer 44a.

Next, ion implantation 48 is performed to form a lightly doped drain region 46 in the semiconductor substrate 40 exposed on both sides of the gate structure 42 of the photoresist layer 44. After removing the photoresist layer 44, Figure 4C shows. Here, the energy used for ion implantation of the lightly doped drain may be 100 keV to 200 keV.

Referring to FIG. 5, the width of the gate structure 42 is L, the width of the first photoresist layer 44a is S, and the ratio of the width S to the width L (S/L) is 3/4 in the example of the present invention. ~5/8; For example, S/L may generally be 0.6 μm / 0.8 μm, preferably 0.55 μm / 0.8 μm, more preferably 0.5 μm / 0.8 μm. In addition, the first side portion SP1 and the second side portion SP2 of the gate structure 42 exposed on both sides of the first photoresist layer 44a may have the same width B, but may have different widths. The width B is also the distance between the edge of the first photoresist layer 44a and the edge of the gate structure 42. Further, the width S is larger than the width B, and when the first side portion SP1 and the second side portion SP2 have the same width B, L = S + 2B.

6 to 8 are views showing electrical characteristics of a MOS transistor having a lightly doped drain obtained by applying the manufacturing method of the semiconductor device of the present invention.

Fig. 6 is a graph showing the characteristics of the substrate current Isub of the MOS transistor with respect to the gate voltage Vgate. In Fig. 6, the lightly doped gates of the MOS transistors corresponding to the curves 61 and 62 are formed in the layout of Fig. 2, and the widths of the gate structures are 0.8 μm and 0.85 μm, respectively; The lightly doped gate of the corresponding MOS transistor is formed in the layout of the fifth embodiment of the present invention, and the width of the gate structure is 0.8 μm. As is apparent from Fig. 6, the apex value of the substrate current |Isub| can be lowered from about 52 μA/μm of the curve 61 to about 36 μA/μm by applying the present invention. It is worth noting that even if the MOS transistor of the curve 63 does not increase the width L (0.8 μm) of the gate structure, its performance of lowering the substrate current Isub is better than that of the MOS transistor of the curve 62 (the width L is increased to 0.85 μm). ).

Fig. 7 is a graph showing the characteristic of the drain current Idrain of the MOS transistor with respect to the gate voltage Vdrain. In Fig. 7, the lightly doped gate of the MOS transistor corresponding to the curve 71 is formed in the layout of Fig. 2, and the width of the gate structure is 0.8 μm; the MOS transistor corresponding to the curve 72 The lightly doped drain is formed by the layout of the fifth embodiment of the present invention, and the width of the gate structure is 0.8 μm. It can be seen from the results of FIG. 7 that the drain current Idrain of the MOS transistor corresponding to the curve 72 is larger than the drain current of the MOS transistor corresponding to the curve 71, that is, the current driving capability of the MOS transistor of the curve 72 is better. The current drive capability of the MOS transistor of curve 71. Therefore, the application of the present invention does not detract from the current drive capability of the MOS transistor.

Fig. 8 is a graph showing the breakdown voltage characteristics of the MOS transistor. In Fig. 8, the lightly doped gate of the MOS transistor corresponding to the curve 81 is formed in the layout of Fig. 2, and the width of the gate structure is 0.8 μm; the MOS transistor corresponding to the curve 82 The lightly doped drain is formed by the layout of the fifth embodiment of the present invention, and the width of the gate structure is 0.8 μm. The horizontal axis of Fig. 8 represents the drain voltage Vdrain, and the vertical axis represents the logarithmic drain leakage current log (Idrain). As is apparent from the results of Fig. 8, the application of the present invention does not impair the collapse characteristics of the MOS transistor.

In the layout shown in FIG. 2, the semiconductor substrate is ion-implanted with a single opening (20) to fabricate a lightly doped drain; and the present invention has two openings in the layout shown in FIG. The parts (SP1, SP2) fabricate the light-doped drain of the semiconductor substrate, which can effectively reduce the substrate current without increasing the width L of the gate structure and avoid reducing the current driving capability of the MOS transistor. In addition, it does not affect the breakdown characteristics of MOS transistors.

Claims (10)

 A semiconductor manufacturing method comprising: forming a gate structure on a semiconductor substrate; forming a photoresist layer on the gate structure, the photoresist layer having at least a narrow portion, the narrow portion having a width smaller than a width of the gate a first side portion and a second side portion of the gate are exposed on both sides of the photoresist layer; and ion implantation is performed to form light doping in the semiconductor substrate on both sides of the gate structure Bungee area.    The semiconductor manufacturing method of claim 1, wherein a width of the narrow portion of the photoresist layer is S, a width of the gate structure is L, an edge of the narrow portion and an edge of the gate structure The distance is B and S>B.    The semiconductor manufacturing method of claim 1, wherein the first side portion and the second side portion respectively exposed on both sides of the photoresist layer have substantially equal widths B.    The semiconductor manufacturing method according to claim 3, wherein the narrow portion of the photoresist layer has a width S, the gate structure has a width L, and L, B, and S respectively conform to L=S+2B. , S>B.    The semiconductor manufacturing method according to claim 1, wherein the energy used for the ion implantation is 100 keV to 200 keV.    A semiconductor manufacturing method comprising: forming a gate structure on a semiconductor substrate; forming a photoresist layer having two openings on the semiconductor substrate by a lithography process using a mask defining two light-transmissive regions And a first photoresist layer located between the two openings is aligned with the gate structure and formed on the gate structure, and the width of the first photoresist layer is smaller than the first photoresist layer a width of the gate structure such that a first side portion and a second side portion of the gate structure are exposed on both sides of the first photoresist layer; and ion implantation is performed to be exposed on the photoresist layer A lightly doped drain region is formed in the semiconductor substrate on both sides of the gate structure.    The semiconductor manufacturing method of claim 6, wherein the first photoresist layer has a width S, the gate structure has a width L, an edge of the first photoresist layer and an edge of the gate structure. The distance is B, and S>B.    The semiconductor manufacturing method of claim 6, wherein the first side portion and the second side portion respectively exposed on both sides of the first photoresist layer have substantially equal widths B.    The semiconductor manufacturing method according to claim 8, wherein the first photoresist layer has a width S, the gate structure has a width L, and L, B, and S respectively conform to L=S+2B, S. >B.    The semiconductor manufacturing method according to claim 6, wherein the energy used for the ion implantation is 100 keV to 200 keV.