TWI713096B - Method of fabricating semiconductor device - Google Patents

Abstract

A method of fabricating a semiconductor device includes the following steps. First, form a gate structure on a semiconductor substrate. Then, use a mask having two transparent regions through a photolithography process to form a photoresist layer having two openings in the semiconductor substrate. A first photoresist layer of the photoresist layer between the two openings is aligned to the gate structure and formed on the gate structure. The width of the first photoresist layer is smaller than that of the gate structure such that a first side portion and a second side portion of the gate structure are not covered by the first photoresist layer. Next, carry out ion implantation to form lightly doped drain regions in the semiconductor substrate which are not covered by the photoresist layer.

Description

Manufacturing method of semiconductor device

The present invention relates to semiconductor devices, in particular to methods for manufacturing lightly doped drain semiconductor devices.

In order to increase the density of components and increase the speed and performance of operation, the size of components is continuously reduced in the manufacturing process of semiconductor devices. Taking the MOS transistor as an example, the vertical electric field and the horizontal electric field increase due to the shortening of the channel length and the decrease of the thickness of the gate oxide layer. As a result of the increase in the horizontal electric field, the speed of carriers in the channel will be accelerated. When these carriers accelerate in the channel to obtain sufficient energy, the probability of these carriers being injected into the gate oxide layer or formed across the oxide layer The gate current, or carrier will generate electron hole pairs at the drain terminal. Therefore, when the channel of the MOS transistor is shortened, the number of carriers close to the drain of the channel will increase and cause the hot electron effect (Hot Electron Effect). In the hot electron effect, part of the electrons are injected into the gate oxide layer, and the corresponding holes generated will flow to the substrate to generate a substrate current. The other part of the holes is collected by the source, which strengthens the phenomenon of the NPN bi-carrier transistor, prompting more carriers to multiply, and even electrical breakdown (Electrical Breakdown) may occur.

Regarding the aforementioned problems, the conventional technology proposes a lightly doped drain (LDD) to slow down or avoid damage to the semiconductor device caused by the hot electron effect. In the semiconductor manufacturing process, the traditional lightly doped drain manufacturing method can still be further improved; and the intention of the present invention is to propose a new manufacturing method for the lightly doped drain.

According to one of the technical features of the present invention, a method of manufacturing a semiconductor device proposed by the present invention includes at least the following steps. First, a gate structure is formed on a semiconductor substrate. Then, a photoresist layer is formed on the gate structure. The photoresist layer has at least a narrow portion, and the width of the narrow portion is smaller than the width of the gate, so that a first side portion and a second side of the gate are The side portions are exposed on both sides of the photoresist layer. Then ion implantation is performed to form lightly doped drain regions in the semiconductor substrate on both sides of the gate structure.

Wherein, the first side portion and the second side portion respectively exposed on both sides of the photoresist layer have substantially the same width B. In addition, the width of the narrow portion of the photoresist layer is S, the width of the gate structure is L, and the aforementioned respective widths L, B, and S meet the specifications of process capability. In addition, the energy used to perform this ion implantation is 100 keV to 200 keV.

According to another technical feature of the present invention, a method of manufacturing a semiconductor device provided by the present invention includes at least the following steps. First, a gate structure is formed on a semiconductor substrate. Using a mask defined with two light-transmitting areas, a photoresist layer with two openings is formed on the semiconductor substrate by a photolithography process; wherein, the photoresist layer is located between the two openings. A first photoresist layer is formed on the gate structure by aligning with the gate structure, and the width of the first photoresist layer is smaller than the width of the gate structure, so that a first side portion of the gate structure And a second side portion is exposed on both sides of the first photoresist layer. Next, ion implantation is performed to form lightly doped drain regions in the semiconductor substrate exposed on both sides of the gate structure of the photoresist layer.

Wherein, the first side portion and the second side portion respectively exposed on both sides of the first photoresist layer have substantially the same width B. In addition, the width of the first photoresist layer is S, the width of the gate structure is L, and L, B, and S meet the specifications of process capability respectively. In addition, the energy used to perform this ion implantation is 100 keV to 200 keV.

Hereinafter, the present invention will be described in detail based on exemplary embodiments and with reference to the accompanying drawings.

10‧‧‧Semiconductor substrate

12‧‧‧Gate structure

12a‧‧‧Gate Oxide

12b‧‧‧Gate

14‧‧‧Photoresist layer

16‧‧‧Lightly doped drain region

18‧‧‧Ion implantation

20‧‧‧Opening area

31-34‧‧‧MOS transistor characteristic curve

40‧‧‧Semiconductor substrate

42‧‧‧Gate structure

42a‧‧‧Gate Oxide

42b‧‧‧Gate

44‧‧‧Photoresist layer

44a‧‧‧First photoresist layer

46‧‧‧Lightly doped drain region

48‧‧‧Ion implantation

OP1-OP2‧‧‧Opening

61-63‧‧‧MOS transistor characteristic curve

71-72‧‧‧MOS transistor characteristic curve

81-82‧‧‧MOS transistor characteristic curve

L‧‧‧The width of the gate structure

S‧‧‧The width of the first photoresist layer

B‧‧‧The width of the first (second) side

SP1‧‧‧First side

SP2‧‧‧Second side

Figures 1A~1C show the manufacturing process of the conventional lightly doped drain.

Figure 2 shows the corresponding layout of Figure 1B.

Figures 3A~3B show the electrical characteristics of the MOS transistor obtained by the layout of Figure 2.

4A to 4C show the manufacturing process of the lightly doped drain according to an embodiment of the present invention.

Figure 5 shows the layout corresponding to Figure 4B.

Figure 6 shows the characteristic diagram of the substrate current Isub of the MOS transistor with respect to the gate voltage Vgate.

Figure 7 shows the characteristic diagram of the drain current Idrain of the MOS transistor with respect to the drain voltage Vdrain.

Figure 8 shows the breakdown voltage characteristics of MOS transistors.

The following descriptions are various implementation examples and aspects of the present invention. Its purpose is to exemplify the general principles of the present invention, and should not be regarded as a limitation of the present invention. The scope of the present invention should be defined by the scope of the patent application.

Figures 1A~1C show the manufacturing process of the conventional lightly doped drain (LDD). In Figure 1A, a gate structure 12 is formed on a semiconductor substrate 10. The semiconductor substrate 10 is, for example, doped-silicon. The gate structure 12 includes a gate oxide layer 12a and The doped-poly gate 12b is not limited to this. In FIG. 1B, a photoresist layer 14 is formed on the semiconductor substrate 10 by using a photomask (not shown) in conjunction with a lithography process. Figure 2 shows the corresponding layout of Figure 1B. It can be seen from FIG. 1B and FIG. 2 that the used photomask (not shown) has a light-transmitting area to define an opening area 20 of the photoresist layer 14 (FIG. 2). Next, ion implantation 18 is performed to form the lightly doped drain region 16, as shown in FIG. 1C after the photoresist layer 14 is removed.

As in the above-mentioned conventional lightly doped drain manufacturing method, most of the gate structure 12 is exposed in the opening area 20 of the photoresist layer 14. Therefore, high-energy ions are easily implanted during high-energy ion implantation. The penetration from the gate structure 12 to the semiconductor substrate 10 will cause drain to source punch-through leakage. In addition, taking the layout structure shown in Figure 2 as an example, the hot electron effect is still very serious in the application of medium voltage (5V~8V). In order to further reduce the hot electron effect, the width of the gate structure 12 is generally increased (and the channel length of the MOS transistor is correspondingly increased) to reduce the lateral electric field in the occasion of high drain voltage. In Fig. 3A, curve 31 represents the characteristics of a MOS transistor with a gate width L of 0.8 μm, and curve 32 represents the characteristics of a MOS transistor with a gate width L of 0.85 μm. As shown in FIG. 3A, as the width L of the gate structure 12 increases, the substrate current Isub decreases accordingly. However, as the width L of the gate structure 12 increases, the size of the semiconductor device and its current driving capability will be affected. In Figure 3B, curve 33 shows the characteristics of a MOS transistor with a gate width L of 0.8μm, and curve 34 shows the characteristics of a MOS transistor with a gate width L of 0.85μm; as shown in Figure 3B, as the gate As the width L of the pole structure 12 increases, the drain current Idrain also decreases.

4A to 4C show the manufacturing process of the lightly doped drain according to an embodiment of the present invention. Figure 5 shows the layout corresponding to Figure 4B.

In FIG. 4A, a gate structure 42 is formed on a semiconductor substrate 40. The semiconductor substrate 40 is, for example, a doped-silicon substrate. The gate structure 42 includes a gate oxide layer 42a and For example, a doped-poly gate 42b is doped, but it is not limited to this.

In Figure 4B, a mask (not shown) defining two light-transmitting regions is used to form a photoresist layer 44 with two openings OP1 and OP2 (Figure 5) on the semiconductor by a photolithography process. On the substrate 40. Wherein, a first photoresist layer 44a of the photoresist layer 42 located between the two openings OP1 and OP2 is aligned with the gate structure 42, and the width S of the first photoresist layer 44a is smaller than the gate. The width L of the structure 42 makes a first side SP1 and a second side SP2 of the gate structure 42 exposed on both sides of the first photoresist layer 44a.

Next, ion implantation 48 is performed to form lightly doped drain regions 46 in the semiconductor substrate 40 exposed on both sides of the gate structure 42 of the photoresist layer 44. After the photoresist layer 44 is removed, such as As shown in Figure 4C. Here, the energy used for ion implantation of lightly doped drain can be 100keV~200keV.

Referring to FIG. 5, the width of the gate structure 42 is L and the width of the first photoresist layer 44a is S. In the example of the present invention, the ratio (S/L) of the width S to the width L is 3/4 ~5/8; For example, S/L can generally be 0.6μm/0.8μm, preferably 0.55μm/0.8μm, more preferably 0.5μm/0.8μm. In addition, the gate structure 42 exposed on both sides of the first photoresist layer 44a may have the same width B of the first side portion SP1 and the second side portion SP2, but may also have different widths. The width B is the distance between the edge of the first photoresist layer 44a and the edge of the gate structure 42. Moreover, the width S is greater than the width B, and when the first side portion SP1 and the second side portion SP2 have the same width B, L=S+2B.

Figures 6 to 8 show electrical characteristic diagrams of MOS transistors with lightly doped drains obtained by applying the semiconductor device manufacturing method of the present invention.

Figure 6 shows the characteristic diagram of the substrate current Isub of the MOS transistor with respect to the gate voltage Vgate. In Figure 6, the lightly doped drains of the MOS transistors corresponding to curves 61 and 62 are formed in the layout of Figure 2, and the widths of their gate structures are 0.8 μm and 0.85 μm, respectively; as shown in curve 63 The lightly doped drain of the corresponding MOS transistor is formed by the layout of FIG. 5 disclosed in the present invention, and the width of the gate structure is 0.8 μm. It is obvious from Fig. 6 that the application of the present invention can reduce the peak value of the substrate current |Isub| from about 52 μA/μm of the curve 61 to about 36 μA/μm. It is worth noting that even though the MOS transistor of curve 63 does not increase the width L (0.8 μm) of the gate structure, its performance in reducing the substrate current Isub is better than that of the MOS transistor of curve 62 (the width L is increased to 0.85 μm) ).

Figure 7 shows the characteristic diagram of the drain current Idrain of the MOS transistor with respect to the drain voltage Vdrain. In Figure 7, the lightly doped drain of the MOS transistor corresponding to curve 71 is formed in the layout of Figure 2, and the width of its gate structure is 0.8μm; the lightly doped drain of the MOS transistor corresponding to curve 72 is The lightly doped drain is formed by the layout of Figure 5 disclosed in the present invention, and the width of the gate structure is 0.8 μm. From the results in Figure 7, it can be seen that the drain current Idrain of the MOS transistor corresponding to curve 72 is greater than the drain current of the MOS transistor corresponding to curve 71, that is, the current drive capability of the MOS transistor of curve 72 is better than The current drive capability of the MOS transistor in curve 71. Therefore, the application of the present invention will not impair the current drive capability of the MOS transistor.

Figure 8 shows the breakdown voltage characteristics of MOS transistors. In Figure 8, the lightly doped drain of the MOS transistor corresponding to curve 81 is formed in the layout of Figure 2, and the width of its gate structure is 0.8 μm; the MOS transistor corresponding to curve 82 The lightly doped drain is formed by the layout of Figure 5 disclosed in the present invention, and the width of the gate structure is 0.8 μm. The horizontal axis of Figure 8 represents the drain voltage Vdrain, and the vertical axis represents the drain leakage current log(Idrain), which is a logarithmic value. It is obvious from the results in Fig. 8 that the application of the present invention will not damage the breakdown characteristics of the MOS transistor.

In the layout shown in Figure 2, a single opening (20) is used to fabricate lightly doped drain ion implantation on the semiconductor substrate; while the present invention uses the layout shown in Figure 5 to use two openings The parts (SP1, SP2) implant the lightly doped drain on the semiconductor substrate, which can effectively reduce the substrate current without increasing the width L of the gate structure to avoid reducing the current driving capability of the MOS transistor. In addition, it will not affect the breakdown characteristics of the MOS transistor.

42‧‧‧Gate structure

44‧‧‧Photoresist layer

44a‧‧‧First photoresist layer

OP1-OP2‧‧‧Opening

L‧‧‧The width of the gate structure

S‧‧‧The width of the first photoresist layer

B‧‧‧The width of the first (second) side

SP1‧‧‧First side

SP2‧‧‧Second side

Claims (10)

A semiconductor manufacturing method includes: forming a gate structure on a semiconductor substrate, wherein the gate structure includes a polysilicon gate and a gate oxide layer formed under the polysilicon gate; forming a photoresist layer on the On the polysilicon gate of the gate structure, wherein the width of the photoresist layer is smaller than the width of the gate structure, so that the polysilicon gate of the gate structure partially contacts the photoresist layer and a part of the gate oxide layer The first side portion and the second side portion are exposed on both sides of the photoresist layer; and ion implantation is performed when the width of the gate structure is greater than the width of the photoresist layer, so as to be on both sides of the gate structure A lightly doped drain region is formed in the semiconductor substrate, and the photoresist layer is removed. The semiconductor manufacturing method as described in item 1 of the scope of patent application, wherein the width of the photoresist layer is S, the width of the gate structure is L, and the distance between the edge of the photoresist layer and the edge of the gate structure is B , And S>B. The semiconductor manufacturing method described in claim 1, wherein the first side portion and the second side portion of the gate oxide layer exposed on both sides of the photoresist layer respectively have substantially equal width B . As for the semiconductor manufacturing method described in item 3 of the scope of patent application, the width of the photoresist layer is S, the width of the gate structure is L, and L, B, and S respectively meet L=S+2B, S>B . The semiconductor manufacturing method described in the first item of the scope of patent application, wherein the energy used for the ion implantation is 100keV~200keV. A semiconductor manufacturing method includes: forming a gate structure on a semiconductor substrate, wherein the gate structure includes a Polysilicon gate and a gate oxide layer formed under the polysilicon gate; using a mask that defines two light-transmitting regions, a photoresist layer with two openings is formed on the semiconductor substrate by a photolithography process On; wherein, a first photoresist layer of the photoresist layer located between the two openings is aligned with the gate structure to form and partially contact the polysilicon gate of the gate structure, and the first The width of a photoresist layer is smaller than the width of the gate structure, so that a first side and a second side of the gate structure are exposed on both sides of the first photoresist layer; and at the width of the gate When the width of the first photoresist layer is larger than the photoresist layer, ion implantation is performed to form lightly doped drain regions in the semiconductor substrate exposed on both sides of the gate structure of the photoresist layer, and remove The photoresist layer. The semiconductor manufacturing method described in item 6 of the scope of patent application, wherein the width of the first photoresist layer is S, the width of the gate structure is L, the edge of the first photoresist layer and the edge of the gate structure The distance is B, and S>B. According to the semiconductor manufacturing method described in claim 6, wherein the first side portion and the second side portion of the gate oxide layer exposed on both sides of the first photoresist layer have substantially equal Width B. The semiconductor manufacturing method described in item 8 of the scope of patent application, wherein the width of the first photoresist layer is S, the width of the gate structure is L, and L, B, and S meet L=S+2B, S >B. The semiconductor manufacturing method described in item 6 of the scope of patent application, wherein the energy used for the ion implantation is 100keV~200keV.

Images