TW201928340A - Nanoelectrode devices and methods of fabrication thereof - Google Patents

Abstract

The present disclosure provides devices and methods for fabrication of nanoelectrode pairs which may be useful for use with tunneling labels. Devices fabricated as described may have good spacing tolerances, angular tolerances, surface uniformity, and may have reduced particulate contamination.

Description

Nano electrode device and manufacturing method thereof

Various methods have been used to make the electrode gap. But these devices (such as MCBJ (Mechanical Interrupt Interface)) and methods limit the number of sensors that can be implemented on a single chip, and there are problems with yield, tolerance, background level, and uniformity of the gap width .

Electrode pairs and associated gaps can be used as detectors for direct detection of tunneling current or detection using tunneling marks; similarly, electrode pairs and associated gaps can be used for direct detection of electrochemical species or electrochemical labels Detect.

Manufacturing of millions or billions of functional sensors that can be expected to be used on a single integrated circuit requires improved programming methods and the resulting sensors.

This article recognizes the need for highly accurate and low cost efficient and rapid measurement of native DNA bases.

Some aspects of the present invention provide an apparatus including at least two electrodes disposed on a substrate separated by a non-conductive gap. The electrodes and the gap may be configured to accommodate a portion such as a polymerase, a reducing species, or any other suitable portion.

In some embodiments, the at least one electrical signal is at least partially a non-Faradaic current. In some embodiments, the at least one signal includes a plurality of signals. In some embodiments, the at least one signal may include a tunneling current or a tunneling current and a skip current. In some embodiments, one or more labeled nucleotide types can be labeled using one or more molecules or other moieties that can facilitate the formation of a tunneling current and / or a jump current. In some embodiments, one or more molecules and / or other portions may include a conductive portion. In some embodiments, a conductive portion allows a current to pass through it when one or more molecules or other portions experience a potential. In some embodiments, a current may be direct current (DC). In some embodiments, a current may be alternating current (AC). In some embodiments, a molecule may include a tunneling tag. In some embodiments, a tunneling mark may be combined with a target portion, and the tunneling mark may be used to detect the target portion. In some embodiments, a tunneling tag can include a nucleic acid sequence. In some embodiments, at least one electrical signal can be detected with a signal-to-noise ratio greater than or equal to about 100: 1. In some embodiments, a signal-to-noise ratio may be greater than or equal to about 1000: 1. In some embodiments, at least one electrical signal can be detected in real time.

In some embodiments, a gap width or interval may be less than or equal to about 20 nm. In some embodiments, a gap width or interval may be greater than 20 nm. In some embodiments, a flow channel may have a depth greater than or equal to about 100 nm. In some embodiments, a sensor having at least two electrodes may have a first portion and a second portion adjacent to and under the first portion. In some embodiments, a first portion may have a first width, and a second portion may have a second width that is less than one of a first width. In some embodiments, a sensor may have a cross-sectional shape of an inverted cone.

Another aspect of the present invention provides a system for sequencing a nucleic acid molecule, comprising: a substrate including at least two electrodes separated by a gap as a part of a flow channel, wherein a substrate may be A solid; and a computer processor operatively coupled to a substrate and programmed to perform the steps required for detection, which may further include chemical and / or biochemical steps.

In some embodiments, the at least one electrical signal may be at least partially an illegal Radian current. In some embodiments, the at least one signal may include a plurality of signals. In some embodiments, the at least one electrical signal may include a tunneling current. In some embodiments, a tag may include a molecule that promotes the formation of a tunneling current and a jump current. In some embodiments, a tag may include a conductive portion. In some embodiments, when a mark can withstand a potential, a conductive portion may allow a current to pass through it. In some embodiments, a current may be direct current (DC). In some embodiments, a current may be alternating current (AC).

In some embodiments, a current may be a combination of direct current and alternating current. In some embodiments, a molecule may include a tunneling tag. In some embodiments, a tunneling tag can be bound to a base portion of a given nucleotide type of one or more labeled nucleotide types. In some embodiments, a tunneling label can be bound to one of the one or more labeled nucleotide types, a phosphate chain of a given nucleotide. In some embodiments, a tunneling label may be bound to any position of a set of one or more labeled nucleotide types of a given nucleotide, such as ribose or other backbone molecule. In some embodiments, a tunneling tag is reversibly bound to a given nucleotide of one or more labeled nucleotide types. In some embodiments, one or more labeled nucleotide types may include at least two different types of nucleotides or variants thereof. In some embodiments, a different tunneling label can be used to label each type of at least two types of nucleotides or variants thereof.

In some embodiments, at least one electrical signal can be detected with a signal-to-noise ratio greater than or equal to about 100: 1. In some embodiments, a signal-to-noise ratio may be greater than or equal to about 1000: 1. In some embodiments, at least one electrical signal can be detected in real time.

In some embodiments, a gap may be greater than or equal to about 1 nanometer (nm). In some embodiments, a gap width or spacing associated with a pair of nanoelectrode pairs described below may be less than or equal to about 20 nm. In some embodiments, a flow channel has a depth greater than or equal to about 100 nm.

In some embodiments, a sensor including an electrode pair may have a first portion and a second portion adjacent to and under a first portion. In some embodiments, a first portion may have a first width, and a second portion may have a second width that is less than one of a first width. In some embodiments, a polymerase may have a size larger than the second width and smaller than one of the first width. In some embodiments, a sensor including an electrode pair may have a cross-sectional shape of an inverted cone.

In some embodiments, a system may further include a chip having a sensor, and the sensor having a substrate. In some embodiments, at least two electrodes may be coupled to a circuit. In some embodiments, a sensor may be coupled to a circuit that processes at least one electrical signal. In some embodiments, a wafer may include a plurality of sensors, each of which includes a separate electrode pair. In some embodiments, a wafer may include at least about 10,000, about 100,000, about 1,000,000, about 10,000,000, about 100,000,000, about 1,000,000,000, about 10,000,000,000, or more than 10,000,000,000 sensors. In some embodiments, each of the plurality of sensors or the plurality of array sensors may be independently addressed.

In some embodiments, the at least one electrical signal may be an illegal Radian current. In some embodiments, the at least one signal may include a plurality of signals. In some embodiments, the at least one electrical signal may include a tunneling current. In some embodiments, one or more labeled nucleotide types can be labeled using a molecule and / or other portions that can facilitate the formation of a tunneling current or tunneling and hopping current.

In some embodiments, the at least one electrical signal may be at least partially an illegal Radian current. In some embodiments, the at least one signal may include a plurality of signals. In some embodiments, the at least one electrical signal may include a tunneling current. In some embodiments, one or more labeled nucleotide types may be labeled using a molecule that promotes the formation of a tunneling current or tunneling and hopping current. In some embodiments, a molecule may include a tunneling tag.

Those skilled in the art will readily understand additional aspects and advantages of the present invention from the [Embodiment], and only the illustrative embodiments of the present invention are shown and described in [Embodiment]. It should be appreciated that the invention is capable of other and different embodiments, and that several details of the invention can be modified in various obvious respects, all of which should not depart from the invention. Accordingly, the drawings and [embodiments] are to be regarded as illustrative rather than restrictive. Incorporate by reference

All publications, patents, and patent applications mentioned in this specification are incorporated herein by reference as if each individual publication, patent, or patent application was specifically and individually indicated to be incorporated by reference.

Cross reference

This application claims the rights of US Provisional Patent Application No. 62 / 563,859, filed on September 27, 2017, the entirety of which is incorporated herein by reference.

Although various embodiments of the invention have been shown and described herein, those skilled in the art will appreciate that these embodiments are for illustration only. Those skilled in the art can think of many variations, changes, and substitutions without departing from the present invention. It should be understood that various alternatives to the embodiments of the invention described herein may be employed.

As used herein, the term "gap" generally refers to a volume, space, hole, channel, or pathway formed or otherwise provided in a material or between electrodes. The material may be a solid material such as a substrate or may be formed from different layers formed on a substrate. A gap may be positioned adjacent to or close to a sensing circuit or coupled to an electrode of a sensing circuit. In some examples, a gap may have a feature width or diameter of about 0.1 nanometers (nm) to about 1,000 nm. A gap with a nanometer width can be referred to as a "nano gap" (also referred to herein as a "nano gap"). In some cases, a one nanometer gap may have a thickness of from about 0.1 nanometers (nm) to about 50 nm, 0.5 nm to 30 nm or 0.5 nm to 10 nm, 0.5 nm to 5 nm, or 0.5 nm to 2 nm, 5 nm to 30 nm, 10 nm to 20 nm, 5 nm to 20 nm, 15 nm to 25 nm or not greater than about 2 nm, about 1 nm, about 0.9 nm, about 0.8 nm, about 0.7 nm, about 0.6 nm or One width or interval of about 0.5 nm. In some cases, the one nanometer gap has at least about 0.5 nm, about 0.6 nm, about 0.7 nm, about 0.8 nm, about 0.9 nm, about 1 nm, about 2 nm, about 3 nm, about 4 nm, and about 5 nm. nm, about 7.5 nm, about 10 nm, about 15 nm, about 20 nm, about 30 nm, or a width greater than 30 nm. In some cases, the width or spacing of a nano-gap may be larger than a diameter of a biomolecule used in a sequence reaction or may be smaller than a sample biomolecule or a subunit (e.g., a monomer) of a sample biomolecule. Of its diameter.

As used herein, the terms "adjacent" or "adjacent to" include "immediately", "adjacent", "contacting", and "close to". In some examples, neighboring components are separated from each other by one or more intervening layers. For example, one or more intervention layers may have a thickness of less than about 10 micrometers ("μm"), 1 μm, 500 nanometers ("nm"), 100 nm, 50 nm, 10 nm, 1 nm, or less. In one example, when a first layer is in direct contact with a second layer, the first layer is adjacent to the second layer. In another example, when a first layer is separated from a second layer by a third layer, the first layer is adjacent to the second layer.

As used herein, the term "tunneling" generally refers to a particle such as an electron moving through a potential barrier. If the particle does not have sufficient energy, it cannot overcome the potential barrier. This can be compared to standard conductance, where a particle can have enough energy to overcome any energy barriers.

As used herein, the term "tunneling mark" generally refers to a portion (such as a compound, a molecule, a Particles and combinations thereof). In some cases, the tunneling can be measured as a tunneling and / or jumping current.

As used herein, the term "tunneling current" generally refers to a current signal associated with the tunneling of electrons or holes between two electrodes to which a voltage (eg, a bias voltage) is applied. Tunneling can enter, leave, pass through a tunneling mark, or any combination thereof. In some cases, tunneling may be combined with a portion of one of the conduction paths in which a jump may occur.

The invention provides a device and a method related to the formation of the device. The device has a gap or a gap group formed by a pair of electrodes or a group of electrode pairs that can be used to identify a tunneling signal or an electrochemical signal. Sensor electrode

One system of the present invention may be a highly scalable system. For example, millions or billions of sensors can be placed on a single wafer that is similar in size to one of the current DNA sequencing electronic sensors. Current DNA sequencing electronic sensors include two separated by a gap. The electrodes and one on a single device have a very small pitch. In some cases, a wafer may have a very high density of one of the sensors. For example, a single wafer may have a sensor density greater than or equal to one of: about 5,000, about 10,000, about 20,000, about 30,000, about 40,000, about 50,000, and about 60,000 per square inch. About 70,000, about 80,000, about 90,000, about 100,000, about 200,000, about 300,000, about 400,000, about 500,000, about 600,000, about 700,000, about 800,000, about 900,000, about 1,000,000, approximately 2,000,000, approximately 3,000,000, approximately 4,000,000, approximately 5,000,000, approximately 6,000,000, approximately 7,000,000, approximately 8,000,000, approximately 9,000,000, approximately 10,000,000, approximately 20,000,000, approximately 30,000,000, approximately 40,000,000 About 50,000,000, about 60,000,000, about 70,000,000, about 80,000,000, about 90,000,000, about 100,000,000, about 200,000,000, about 300,000,000, about 400,000,000, about 500,000,000, about 600,000,000, about 700,000,000, about 800,000,000, about 900,000,000, about 1,000,000,000, about 2,000,000,000, about 3,000,000,000, about 4,000,000,000, about 5,00 0,000,000 or more sensors. In some cases, older modes of circuit processing can be utilized, making it possible to manufacture a variety of custom wafer designs without increasing the cost of state-of-the-art high-density modes, such as the 14 nm or the upcoming 10 nm mode. In some cases, one density of the sensors may not be limited to optical or diffuse crosstalk.

In some cases, a massively parallel design using one of the wafers of a lithography process can be used to place a large number of sensors on a substrate. Each sensor may have two electrodes separated by a gap. Individual sensors can be separated up to a pitch size. The size of one pitch on the X-axis and Y-axis can be the same or different. Each sensor may have a unique or multiplexed electronic path to apply a bias voltage between electrodes on an electrode pair and / or read a tunneling current. Thus, each electrode can be individually addressed and read or read in groups (eg, in columns), where an analog-to-digital converter can exist in each row. In some cases, there may be multiple analog-to-digital converters associated with each row (e.g., at opposite ends of a row), or multiple analog-to-digital converters may be interspersed within a row. The electrodes on each sensor can be made of gold, platinum, copper, palladium, silver or other coined metals or precious metals or graphene. The use of a coin metal or a noble metal can facilitate the bonding of thiol groups to the electrode.

In some cases, the size of a gap between the electrodes included in the sensor can be designed so that the electrodes can be parallel or at 1 °, 2 °, 3 °, 4 °, 5 °, 6 °, 7 °, 8 °, 9 ° or 10 ° parallel. The electrode can also be designed to have a gap so that the SAM can be placed on the electrode, and an enzyme can be fitted between the SAM layers, and the SAM layer is bonded to an electrode in a gap between them.

As shown in FIG. 3W, in some cases, the electrodes or a structure associated with the electrodes may be angled relative to each other, and may be formed using a KOH etch to create a chamfered cone. The electrode pairs 342A and 342B associated therewith may form an angle with respect to each other, or may be made parallel or opposite sides substantially as described above. A structure may have an entrance (which may have a width sufficient to allow a polymerase or other enzyme 330 to enter a width), and have an inclined surface 340 (which would be too narrow to allow a polymerase to fit between them), It may further have an electrode, and the electrode may have a space that may be significantly narrower than a polymerase or other enzyme 330, so that a label shorter than a diameter of a polymerase or other enzyme may be used.

In some cases, the size of a gap between the electrodes can be narrower or smaller than about 10 nm to allow for measurement of conductance using a nucleic acid label with 30 base pairs. In some cases, a gap can be larger or wider than about 2 nm to about 3 nm to avoid TLF false positives and easy to manufacture.

In some cases, a set of fluid channels can be used to distribute reagent sets, enzymes, and / or polymerases to electrode pairs disposed on or near a substrate. In some cases, a fluid channel may have a width corresponding to a physical readout configuration of a wafer, such as several columns per multiplexer amplifier. A fluid channel may have a height sufficient to easily supply reagents and enzymes, which may be the following heights: 100 nm to 200 nm, 200 nm to 500 nm, 500 nm to 1 μm, 1 μm to 5 μm, 5 μm to 10 μm , 10 μm to 50 μm, 50 μm to 250 μm, or greater than 250 μm. The width of a fluid channel can be made relatively narrow, and it can also have a width that can correspond to hundreds or thousands of sensors. Therefore, a height and a tolerance can significantly cover the entire wafer than a fluid channel. When tight. In other cases, a gap (eg, a nano gap) associated with a sensor may be wider than an enzyme or a polymerase. The width of an enzyme or polymerase can be regarded as the smallest size of an enzyme or polymerase, where an enzyme or polymerase can be complexed with a part of single-stranded and part-double-stranded nucleic acids, and the thumb of an enzyme or polymerase can be opposite Open in the palm of an enzyme or polymerase. A nucleic acid strand may be bound to an enzyme or polymerase or to an enzyme or polymerase and complex with a length of a nucleic acid moiety. An axis may be aligned with a metal surface including a gap or nanogap. parallel. In some cases, at least one electrode of an electrode pair may be covered by a dielectric, partially or not covered by a dielectric, and a second member of a pair may be covered by a dielectric, covered by a dielectric The dielectric is partially covered or not covered by a dielectric.

In some cases, a sensor may include an electrode pair. An electrode pair can be configured to detect tunneling or tunneling and jump marks, or it can be used to directly detect a target portion. In a further case, instead of using a gap as will be described below, an electrode pair can be formed without creating a gap or nano-gap, but except that one RIE step for forming a gap may not be performed, An electrode pair can be formed in a similar manner. In these cases, the active areas of the electrodes may be substantially coplanar. In those cases where a polymerase, enzyme, or other part used in a measurement can bind to a dielectric that can form a gap between a sensing electrode and a bias electrode, a ratio is required A polymerase, enzyme, or other moiety is bound at a midpoint between a sensing electrode and a bias electrode in a manner that forms a bond that is associated with the length of a marker and / or a marker The agent takes into account the tolerance for position binding and movement of the polymerase, enzyme, or other parts used in a measurement. Additional tolerances that may be considered may include, for example, diffusion relative to binding points for a polymerase, enzyme, or other part used in a measurement, due to the length attributable to a linker To allow for diffusional movement, a polymerase, enzyme, or other part used in a measurement can be allowed or rotated by a linker to allow a polymerase, enzyme, or other part used in a measurement.

In some cases, a triplet, quadruple, or array of electrodes (eg, a linear array) may be used in place of a pair of electrodes. The electrodes can be configured in a configuration such that the electrodes can be substantially coplanar and have the same or different distances between different electrodes.

In some cases, the electrode can be covered or partially covered by a dielectric, so that a DC current can be minimized and cannot be measured in some cases, but an AC field can be applied and a tunneling current and any capacitive current can be determined. This may allow the use of tunneling and / or jump current detection and separation by alternative methods, such as electrophoretic separation, where the field associated with the electrophoretic separation would otherwise affect the tunneling current and / or bind to the tunneling electrode because The potential associated with an electrophoretic field cannot be properly determined or controlled or may change.

In some cases, the kinetic energy detection described above (which can be the kinetic energy detection of multiple molecules or the detection of several copies that can be fixedly combined) can be used to achieve detection and quantification. In some cases, a dynamic range can be expanded by increasing the number and / or size of one of the electrode pairs.

In some embodiments shown in FIG. 1A to FIG. 1K, a sensor pair including a pair of electrodes and a nanometer gap can be formed, and a metal deposition cone angle can be controlled so that an angle of the deposited metal can be changed across Different ways of depositing different metal deposits on a wafer (regardless of how the angle of the metal emitted from the metal source changes) is one way to form a sensor pair including a pair of electrodes and a nanometer gap. In addition, the use of a double-layered photoresist mask on both sides of one of the deposited metal areas can minimize or eliminate the formation of metallic nano particles.

FIG. 1A shows the initial steps for manufacturing a two-electrode and nano-gap device, in which a substrate 101 is covered by a first deposited dielectric layer 102, which may be a silicon nitride layer or a silicon oxide layer or other desired dielectric layer. It is then covered by a second dielectric layer 103 which may be a silicon nitride layer or a silicon oxide layer or other desired dielectric layer. The substrate may be a bare silicon wafer or other similar substrate, or may be an integrated circuit already formed thereon and then having applied and planarized (using, for example, a CMP (Chemical Mechanical Polishing) procedure or other procedure) A silicon oxide layer to provide a wafer with a suitable flat surface for subsequent formation of a nano-gap sensor. If the wafer is a nominal bare substrate, an oxidation process can be used to form a surface oxide.

(Several) additional adhesive layers (not shown) may be formed between the substrate 101, the first dielectric layer 102 or the second dielectric layer 103 or the substrate 101, the first dielectric layer 102 or the second dielectric layer 103 And may include any suitable dielectric layer; an additional adhesive layer may include (but is not limited to) a chromium-based material (Cr, Cr ₂ O _3, etc.), a titanium-based material (e.g. Ti, TiO ₂ etc.) Etc.), Al, Al ₂ O ₃ , Ta, Cu, Pb, amorphous silicon, GaAs, other semiconducting materials, chalcogen glass (which can also be amorphous, doped metal or doped rare earth metal) and oxidation Indium tin (ITO). This additional adhesive layer may be used with any of the layers described herein as needed, and different adhesive layers may be used in different steps of a method or procedure associated with different layers or materials to be adhered.

In FIG. 1B, a double-layer photoresist is formed, wherein the thickness of the first photoresist layer 104 can be used as an upper limit of the thickness of the subsequent first metallization layer. The second photoresist layer 105 can be made to have an open void that can be substantially the same size as the top of the first metallization layer. The thickness of the second photoresist layer 105 combined with the width of the pores in the second photoresist layer 105 forming the width of the first metallization layer forms the cone angle of the metal deposition. The taper angle can be set to any desired angle that can be less than the width of the initial taper angle of the deposition source.

Next, a first metallization layer 106 may be deposited, where a cone angle may correspond to a relationship between the pore width and the thickness of the second photoresist layer 105, as shown in FIG. 1C. The metallization layer may be thinner than the thickness of the first photoresist layer 104 to prevent the first metallization layer from reaching the bottom of the second photoresist layer 105 and thus prevent the first metallization layer from being accidentally deposited on the second photoresist layer 105. The material on the side of the aperture (not shown) creates sharp edges. FIG. 5 shows an exemplary TEM of one of the exemplary first metallization layers; the measurement angle varies with a cross-wafer angle of less than 4 ° relative to a perpendicular to a surface, which can therefore be used to form a cone angle that is significantly smaller than the metal-free deposition cone One of the changes in control is the nano-gap; TEM also shows the absence of metal nano-particles that were observed during the control of the cone angle of the previous metal-free deposition and shown in Figure 3F.

The interval between the first photoresist layers 104 can be wider than the expected first metallization layer, and the interval between the first photoresist layers 104 can be wider than the width of the first metallization layer at the base of the first metal.

The side of the first photoresist layer 104 is deposited by making the size equal to or slightly smaller than the width of the bottom edge of the trapezoid of the first metallization layer 106 deposited.

One of the first metallization layers that can be deposited can include any of the above metals suitable for an electrode.

Next, as shown in FIG. 1D, a standard photoresist that may include a first photoresist layer 104 and a second photoresist layer 105 may be implemented to remove the second photoresist layer 105 that has been deposited. Any of the first metallization layer 106 and the first photoresist layer 104 and the second photoresist layer 105. Any first metallization layer that has been deposited on the side of the pores in the second photoresist layer 105 will also be removed. The removal of a double photoresist layer can be performed using a wet process (such as a combination of sulfuric acid and hydrogen peroxide, a combination of ammonia and hydrogen peroxide, or any other suitable wet photoresist removal process), or The removal of the double photoresist layer may be a dry photoresist removal process such as a plasma etch, a reactive ion etch, or an ion beam etch.

The oxide or dielectric layer may be etched using a wet etch that may include buffered hydrofluoric acid etching, KOH etching, hydrofluoric acid etching, phosphoric acid etching, or any other suitable etchant.

A double-layered photoresist pattern can be used to apply an adhesive layer (not shown in the figure), and one of the first photoresist layer 104 and the second photoresist layer 105 can be used before depositing a first metallization layer 107. Layer of photoresist to apply the adhesive layer, or a layer of photoresist that may include one of the first photoresist layer 104 and the second photoresist layer 105 may be applied after depositing a first metallization layer 107, or The adhesive layer may be applied before depositing a first metallization layer and after depositing a first metallization layer using a double photoresist that may include one of the first photoresist layer 104 and the second photoresist layer 105. Alternatively or in combination with the above method of forming an adhesive layer, the first photoresist layer 104 and / or the first photoresist layer 104, the second photoresist layer 105, and the first metallization layer 106 may be removed and removed before forming a first photoresist layer 104 After the first photoresist layer 104, the second photoresist layer 105, and any of the first metallization layer 106 that can be deposited on the second photoresist layer 105 or the first photoresist layer 104, an adhesive layer is applied (not shown in the figure). Show).

In one of the metal deposition sources, a two-layer photoresist (where one of the overhangs of the second layer can otherwise be large enough to allow the formation of nano particles due to the variable rate of the angle of the deposition to the source, as shown in Figure 3F). In some embodiments (shown at the bottom of the nano-gap shown) used together, the formation of metal particles can be prevented by controlling the cone angle, which can also set the angle of one or more sidewalls of the first metallization layer 106. In some embodiments, an aspect ratio may be 1: 2 or greater, 1: 3 or greater, 1: 4 or greater, 1: 5 or greater, 1: 6 or greater, 1: 8 Or larger or 1:10 or larger. The width of one of the pores can be set according to the minimum capabilities of a lithography system (which can be an electron beam lithography system, an optical lithography system, an X-ray lithography system, or any other suitable lithography system). The width of a pore can be less than 3 nm, less than 5 nm, less than 7 nm, less than 10 nm, less than 15 nm, less than 20 nm, less than 25 nm, less than 35 nm, less than 50 nm, less than 70 nm, less than 100 nm, less than 150 nm, less than 250 nm, less than 500 nm, less than 1000 nm, or greater than 1000 nm.

One of the pores in a second photoresist layer 105 may have a square shape (viewed from the top) or may have a rectangular shape (viewed from the top), where all four sides may have a controlled tilt angle and may have a significant reduction or elimination Stray metal particle formation where different side pairs may have different inclination angles and may have significantly reduced or eliminated formation. In other embodiments, a rectangular aperture may be long enough on an axis to protrude below a well structure (as will be described below) so that it can be attributed regardless of being covered by an oxide layer that may be part of a well structure An inclination angle and / or stray metal particles are formed.

In a further embodiment, one of the pores in the second photoresist layer 105 may be non-rectangular, and a portion of the first metallization layer 106 covered by a well structure may be used, for example, to connect to a via to reach a previously formed area described above. The circuit below the nano-gap electrode structure may be connected to a transistor that may be part of an output amplifier unit, or for any other suitable purpose.

In a further embodiment, one of the pores in the second photoresist layer 105 may not be rectangular, but may have a part having a curved surface, a uniform radius or an uneven radius, and a part may also have a shape of a straight segment.

Next, as shown in FIG. 1E, a suitable method (which may include a double photoresist process or may include a single photoresist process, and may include additional metal layer processes such as ion milling) or other standard addition or subtraction processes Or method) to deposit a second metallization layer 107, which may include any of the above metals suitable for an electrode and may further include any metal (such as aluminum or copper) that may be suitable for semiconductor manufacturing. A second metallization layer 107 may be configured to overlap the first metallization layer 106, but may not have the size and shape restrictions required for a first metallization layer 105 to have a controlled sidewall angle and minimize or eliminate otherwise Metal particles may be formed due to a first metallization layer 106. A second metallization layer 107 may be applied relative to a first metallization layer 106 at any rotation angle relative to a vertical axis (as shown in FIG. 1D) and is not limited to the configuration shown in FIG. 1D. Among them, a second metallization layer 107 is shown to extend toward the right of a first metallization layer 106.

A second metallization layer 107 may at least partially cover or at least partially contact a first metallization layer 106, and may be required or desired except for a portion of the first metallization layer 106 to be used as a part of a nano-gap. The second metallization layer 107 is shaped on or in contact with any portion of the first metallization layer 106. A second metallization layer 107 may further include an additional metallization layer that is in contact with a second metallization layer 107 as needed or desired to, for example, provide a common bias potential between multiple sensors.

A second metallization layer 107 may have an adhesive layer (not shown) used therewith and may be applied before depositing a second metallization layer 107 and / or after depositing a second metallization layer 107.

A second metallization layer 107 may have an associated photoresist structure (not shown in the figure) and use the above removal of the photoresist structure and the first metallization layer 106 that has been deposited on the photoresist structure. Any of the methods described to remove any of a second metallization layer 107 that has been deposited on the associated photoresist structure.

Next, as shown in FIG. 1F, a dielectric layer 108 may be applied, wherein the dielectric layer 108 (which may be silicon oxide, silicon nitride, or a metal which may be opposite to a first, second, or third metallization layer) Any other suitable dielectric or other material that is preferentially etched may be applied as a layer on the entire wafer, or a photoresist pattern may be used to apply so that portions of a dielectric layer may be removed in some desired areas. A dielectric layer 108 may be deposited using sputtering, atomic layer film deposition, or any other suitable deposition method. The thickness of one of the dielectric layers 108 can determine the width of a gap between two electrodes consisting of at least one first metallization layer 106 and a third metallization layer, which is strictly based on the thickness or dielectric of one of the dielectric layers 108. A combination of electrical layer 108 and any adhesive layer (which may include the full thickness of an adhesive layer or may include diffusion of an adhesive layer to the metal (s) associated with a first metallization layer 106 or a third metallization layer One of the adhesive layers).

Next, as shown in FIG. 1G, any suitable method (which may include a double photoresist process or may include a single photoresist process and may include additional metal layer processes such as ion milling) or other standard addition or subtraction processes Or method) to deposit a third metallization layer 109, which may include any of the above metals suitable for an electrode and may further include any metal (such as aluminum or copper) that may be suitable for semiconductor manufacturing. A second metallization layer 109 may be configured to overlap the first metallization layer 106, but may not have the size and shape restrictions required for a first metallization layer 105 to have a controlled sidewall angle and minimize or eliminate otherwise Metal particles may be formed due to a first metallization layer 106. A third metallization layer 109 may be applied relative to a first metallization layer 106 at any rotation angle relative to a vertical axis (as shown in FIG. 1D) and is not limited to the configuration shown in FIG. 1D. A third metallization layer 109 is shown as extending toward the left side of a first metallization layer 106.

A third metallization layer 109 may at least partially cover or at least partially contact a first metallization layer 106, and may be shaped as needed or desired. The third metallization layer 109 covers or contacts the first metallization layer 106 covered by the dielectric layer 105. Any part. A third metallization layer 109 may further include an additional metallization layer that is in contact with a third metallization layer 109 as needed or desired to, for example, provide a common bias potential between multiple sensors.

A third metallization layer 109 may have an adhesion layer (not shown) used therewith, and the adhesion layer may be applied before a third metallization layer 109 is deposited and / or after a third metallization layer 109 is deposited.

A third metallization layer 109 may have an associated photoresist structure (not shown in the figure) and use the above removal of the photoresist structure and the first metallization layer 106 that has been deposited on the photoresist structure. Any of the methods described to remove any of the third metallization layer 109 that has been deposited on the associated photoresist structure.

Next, an oxide layer 110 such as silicon oxide, gallium oxide, or any other suitable oxide can be deposited to produce a relatively flat top surface, as shown in FIG. 1H. This oxide layer 110 may be deposited using chemical vapor deposition or other known methods.

Then, a CMP process may be used to planarize the metallization layer, which may include the first metallization layer 106, the second metallization layer 107, and the third metallization layer 109, and remove the deposited metallization layer formed on the first metallization layer. Any gold above a nominal vertical nano-gap between 106 and a third metallization layer 109, as shown in FIG. 1I. A sidewall angle (determined by a sidewall angle of the first metallization layer 106 formed using a control angle described above) may be used to form the first metallization layer 106 and the third metallization layer. A nominal vertical nano-gap between 109.

Next, a second oxide layer 111 such as silicon oxide, gallium oxide, or any other suitable oxide can be deposited to produce a relatively flat top surface, as shown in FIG. 1J. This second oxide layer 111 may be deposited using chemical vapor deposition or other known methods.

As shown in FIG. 1K, a well structure can be formed in the second oxide layer 111, wherein a single layer of photoresist (not shown in the figure) can be wet-formed with one of the second oxide layers 111 described herein. Etching is used together to form a well structure in the second oxide layer 111.

The dielectric layer 108 can be further etched by an etch, wherein the dielectric layer 108 can be exposed by etching the second oxide layer 111 to thereby form a layer between the first metallization layer 106 and the third metallization layer 109. gap. The etching of the dielectric layer 108 may be performed by one of the same wet etch procedures used to etch the second oxide layer 111 to expose the dielectric layer 108 or may be an additional wet etch procedure described herein that may utilize a different etchant Or it may be one of the dry etching procedures described herein.

In some embodiments shown in FIG. 2A to FIG. 2M, a sensor pair including a pair of electrodes and a nanometer gap can be formed, and a metal deposition cone angle can be controlled so that an angle of the deposited metal can be changed across The sensor pair is formed in one way that the different metal depositions of the wafer are more uniform (regardless of the angle of the metal emitted from the metal source). In addition, the use of a tapered photoresist mask can minimize or eliminate the formation of metallic nano particles.

FIG. 2A shows the initial steps for manufacturing a two-electrode and nano-gap device, in which a substrate 201 is covered by a first deposited dielectric layer 202, which may be a silicon nitride layer or a silicon oxide layer or other desired dielectric layer. It is then covered by a second dielectric layer 203, which may be a silicon nitride layer or a silicon oxide layer or other desired dielectric layer. The substrate 201 may be a bare silicon wafer or other similar substrate, or may be an integrated circuit already formed thereon and then may have an applied and planarized (using, for example, a CMP (Chemical Mechanical Polishing) procedure or other procedures) ) To provide a wafer with a suitable flat surface for subsequent formation of a nano-gap sensor. If the wafer includes a nominal bare substrate, an oxidation process can be used to form a surface oxide. In some embodiments, a single dielectric layer may be utilized, wherein the single dielectric layer may include a different material at the top surface of a substrate 201.

After applying a dielectric layer that may include a first dielectric layer 202 and a second dielectric layer 203, an inverted tapered silicon oxide layer 204 may be applied, as shown in FIG. 2C.

After exposure, a tapered etch process such as a plasma ashing process or other dry etch process, or a photoresist tapered process such as described in US4705597, which is incorporated by reference in its entirety, may be utilized ) Or a procedure for forming a tapered waveguide (as described in JP2010-181030 and US2008 / 0299468, the entire contents of which are incorporated by reference) to form the inverted tapered layer 204, which may be described herein Silicon oxide or other oxides or other dielectrics, as shown in Figure 2D.

Next, a first metallization layer 205 may be deposited, wherein one or more edges associated with the current inverted cone layer 204 may be formed at an angle associated with the inverted cone layer 204, as shown in FIG. 2E. The first metallization layer 205 may be thinner than one of the inverted tapered layers 204, or may be thicker than the inverted tapered layer 204, as shown in FIG. 2E.

Sputtering or plating techniques or any other suitable process may be used to form the first metallization layer 205. Any desired layer combination of the adhesive layer and the electrode metal can be used to form the first metallization layer 205.

Then, a CMP process can be used to planarize the first metallization layer 205 and the inverted tapered layer 204, as shown in FIG. 2F.

The inverted tapered layer 204 may then be removed using, for example, a buffered hydrofluoric acid or other suitable etchant as described herein to leave the first metallization layer 205, as shown in FIG. 2G.

Next, as shown in FIG. 2H, a dielectric layer 206 may be applied, wherein the dielectric layer 108 (which may be silicon oxide, silicon nitride, or a metal which may be opposite to a first, second, or third metallization layer) Any other suitable dielectric or other material that is preferentially etched may be applied as a layer above the entire wafer or may be applied using a photoresist pattern so that portions of a dielectric layer may be removed in some desired areas. A dielectric layer 206 may be deposited using sputtering, atomic layer film deposition, or any other suitable deposition method. The thickness of one of the dielectric layers 206 determines the width of a gap between two electrodes composed of at least one first metallization layer 205 and a second metallization layer. A combination of electrical layer 206 and any adhesive layer (which may include the full thickness of an adhesive layer or may include diffusion of an adhesive layer to the metal (s) associated with a first metallization layer 205 or a second metallization layer One of the adhesive layers).

Next, as shown in FIG. 2I, any suitable method (which may include a double photoresist process or may include a single photoresist process and may include additional metal layer processes such as ion milling) or other standard addition or subtraction processes Or method) to deposit a second metallization layer 207, which may include any of the above metals suitable for an electrode. A second metallization layer 207 may be configured to overlap the first metallization layer 205, but it is not necessary to have a tapered photoresist to have a controlled sidewall angle and minimize or eliminate it. 205 and formed metal particles. A second metallization layer 207 may be applied relative to a first metallization layer 205 at any rotation angle relative to a vertical axis (as shown in FIG. 2I) and is not limited to the configuration shown in FIG. 2I A second metallization layer 207 is shown as extending toward the left side of a first metallization layer 205.

A second metallization layer 207 may at least partially cover or at least partially contact a first metallization layer 205 in an area formed by a cone-shaped photoresist and covered by a dielectric layer 206, and then as needed or desired Shape. A second metallization layer 207 or the first metallization layer 205 may further include additional metallization layers that are in contact with a second metallization layer 207 or the first metallization layer 205, respectively, as needed or desired to provide, for example, multiple A common bias potential between the sensors.

A second metallization layer 207 may have an adhesive layer (not shown) used therewith, and the adhesive layer may be applied before a second metallization layer 207 is deposited and / or after a second metallization layer 207 is deposited.

A second metallization layer 207 may have an associated photoresist structure (not shown) and may have any desired shape.

Next, an oxide layer 208 such as silicon oxide, gallium oxide, or any other suitable oxide can be deposited to produce a relatively flat top surface, as shown in FIG. 2J. This oxide layer 208 may be deposited using chemical vapor deposition or other known methods.

Then, a CMP process can be used to planarize the metallization layer that can include the first metallization layer 205 and the second metallization layer 207 and remove the deposited metallization layer formed on the first metallization layer 205 and the second metallization Any gold above a nominal vertical nano-gap between layers 207, as shown in Figure 2K. A tapered photoresist (which is formed using one of the control angles described above) can be used to form a nominal vertical nanometer formed between a first metallization layer 205 and a second metallization layer 207 gap.

Next, a second oxide layer 208 such as silicon oxide, gallium oxide, or any other suitable oxide may be deposited to produce a relatively flat top surface, as shown in FIG. 2L. This second oxide layer 208 may be deposited using chemical vapor deposition or other known methods.

A well structure can be formed in the second oxide layer 208 (as shown in FIG. 2M), wherein a single layer of photoresist (not shown) can be wetted with one of the second oxide layers 209 described herein Etching is used to form a well structure in the second oxide layer 209.

The dielectric layer 206 may be further etched by an etch, wherein the dielectric layer 206 may be exposed by etching the second oxide layer 209 to thereby form a layer between the first metallization layer 205 and the second metallization layer 207. gap. The etching of the dielectric layer 206 may be performed by one of the same wet etch procedures used to etch the second oxide layer 209 to expose the dielectric layer 206, or may be an additional wet etch procedure described herein that may utilize a different etchant Or it may be one of the dry etching procedures described herein.

In some cases, a structure may be manufactured using various standard semiconductor processing methods that may include, for example, each of the following and as shown in FIGS. 3A to 3D: 1) start with a planarized substrate; 2) apply as needed One or more silicon oxide or silicon nitride layers to prevent pinholes that can originate from a single layer. A chemical vapor deposition method can be used to apply the silicon oxide or silicon nitride layer; 3) A photoresist is applied, which can A UV-sensitive mask or an electron beam mask; 4) exposure photoresist, where the exposure can use a standard photomask or can be written using a method such as an electron beam; 5) develop the photoresist; 6) apply A metal layer, which can be applied by a sputtering method, and can include an adhesive layer above and / or below the metal layer, as shown in the top view of FIG. 3A; 7) removing the unnecessary part of the metal layer, which It can be removed by a stripping method; 8) A dielectric layer can be applied, which can be a silicon oxide or silicon nitride layer, and can be applied to have a thickness that can be a desired electrode gap interval, as shown in the bottom view of FIG. 3A Shown in; 9) Apply a photoresist It can be a UV-sensitive mask or an electron beam mask; 10) exposure photoresist, wherein the exposure can use a standard photomask or can use a writing method such as an electron beam; 11) develop the photoresist; 12) Applying a metal layer, which can be applied by a sputtering method, which may include an adhesive layer above and / or below the metal layer; 13) Removing the undesired part of the metal layer, which can be performed using a peeling method Remove, as shown in Figure 3B; 14) apply an oxide layer, which may be silicon oxide or other oxides or dielectrics described herein, and may be thicker than the thickness of the metal layer; 15) a planarized surface, which The required part of the electrode structure can be exposed and can be implemented using a CMP method, as shown in Figure 3C; 16) Applying a dielectric, which can be a silicon nitride or silicon oxide layer, can use a chemical vapor deposition 17) Apply a photoresist, which can be a UV-sensitive photoresist or an electron beam photoresist; 18) Expose a photoresist, where the exposure can use a standard photomask or can use, for example, an electron beam Always write; 19) Make photoresist 20) performing a dry etch or a wet etch, which may utilize any suitable etching procedure or method described herein to form a nano-gap between the electrodes and form a well-like structure over the electrodes; and 21) Remove photoresist, which may include steps, and may include acetone rinse and may include an ashing step, as shown in Figure 3D; 22) use an SPM (sulfuric acid and hydrogen peroxide) to etch or is suitable for selection The other etchant of the adhesive layer comes from the nano-gap to remove the adhesive layer.

In some embodiments where a controlled etch is available, a controlled etch may not reach the bottom of a nano-gap, as shown in FIG. 3D. In some embodiments, thicker metal layers may be utilized, such as greater than 50 nm, greater than 100 nm, greater than 150 nm, greater than 200 nm, greater than 400 nm, or greater than 1000 nm.

In some embodiments in which an adhesive layer can be used between a dielectric layer described in step 8 above and a metal layer described in step 12 above, some adhesive materials such as metal adhesive layers can be combined to improve Etching rate. Therefore, in some embodiments, it may be desirable to apply an adhesive layer only in some areas (such as masking the adhesive layer from areas that can be exposed to a wet etch) so that preventing wet etch can have an increased etch rate.

In other embodiments where a gap can be etched to the bottom and stray nano particles that can be formed during formation of a first metal layer can be removed, a solution that can have weak gold etching capabilities can be used to remove and / Or reduce the size of any stray metal nano particles that have been formed, while removing a small amount of metal from the exposed surface of the electrode.

Figure 3E, Figure 3F, Figure 3G, Figure 3H and Figure 3I show this structure, Figure 3E shows a cross section of a single sensor, and Figure 3F shows a nano gap and a close-up view of one of the two opposing electrodes Figure 3G shows a top well structure in the top oxide layer and a nanometer gap between the two electrodes and the two electrodes (where the crystal grains can be seen in the electrodes). Figure 3H shows several sensors and metal interactions. Figures 3I and 3I show cross sections of this structure at different scales.

In other cases, it can be used to improve the orientation of the crystal grains and can result in having an opposite 111 crystal plane as the opposite surface of the electrode in the electrode gap. One of the initial layers can be a dielectric layer, the first to form a metal layer. An electrode may be formed on the dielectric layer and thus a gap-spaced dielectric, and then a second electrode forming a metal layer is formed to result in the cross-sectional view shown in FIG. 3J, where two electrodes are formed on the first and second electrodes. One of the active surfaces is opposite to the active surface of the first electrode, to the intermediate gap dielectric, then to the active surface of the second electrode, and finally to the second electrode opposite to the active surface area of the second electrode The non-active second surface is in the same deposition direction. Next, a dielectric is deposited and the structure is planarized to result in the structure shown in the cross section of FIG. 3K.

In some cases, it is preferable to center an enzyme, polymerase, or other part that can be used as part of a measurement, or a part that can be used as a part of a measurement, and a size that can be expected to be prevented. The steric hindrance of the function of an enzyme, polymerase, or other part may be expected to produce one or more layers above the active surface of the electrode that is longer (thick) than a SAM that can be used as part of a subsequent measurement. A layer can be formed before binding or attaching an enzyme, polymerase, or other part that is used as part of a measurement procedure (which can be a metal layer, or a dielectric layer or a SAM layer that can be formed by electroplating) ); Therefore, an enzyme, polymerase, or other moiety can be combined or attached to, for example, a dielectric layer that can form a gap between electrodes, and thus can make an enzyme, The polymerase or other part is separated from the electrode; then, the layer for separating an enzyme, polymerase or other part from the electrode can be removed, and therefore a SAM can be bound to the electrode as needed or desired.

In other structures, a structure in which a vertical electrode structure can be used instead of a horizontal electrode structure described above can be formed. For this structure, and as shown in FIG. 3L, an oxide layer may be deposited first, then a first electrode metal layer, then a gap dielectric layer, then a second electrode metal layer, and then a cover dielectric Floor.

Next, as shown in FIG. 3M, an etching pattern is formed that can vertically cut through the top dielectric, the second electrode metal layer, the gap dielectric layer, and can cut through part or all of the second electrode metal layer. An etching process or any other suitable anisotropic etching process is used to perform the etching. Next, as shown in FIG. 3N, a wet etching (which can preferentially etch a gap-interval dielectric) can be performed to thereby form an electrode structure having an opposite 111 crystal plane.

In other cases, a damascene or dual damascene process may be used; starting from a planarized substrate; applying an oxide layer, which may be applied using a chemical vapor deposition method; forming a patterned oxide layer, where An opening is formed in a desired metal volume and a metallization layer is formed over the oxide layer. A CMP process can be used to remove excess metal to leave one of the structures shown in FIG. 3O. The patterned oxide layer can then be removed to leave the structure shown in FIG. 3P. Next, a spacer layer (which may be a silicon nitride layer) may be applied over the structure, as shown in FIG. 3Q. Then, a new patterned oxide layer can be formed, in which an opening is formed next to the first metal volume and above the first metal volume, as shown in FIG. 3R. Then, an additional metal layer may be formed, which includes an additional metal layer remaining in the opening in the second patterned dielectric layer, as shown in FIG. 3S. The structure can then be planarized as shown in Figure 3T. Then, a third patterned oxide layer can be formed using chemical vapor deposition, then a photoresist layer is applied and the photoresist layer is applied, and thus a dry etching is used to leave one of the structures shown in FIG. 3U. A photoresist may be applied again, and a structure shown in FIG. 3V may be formed using a wet or dry etch.

In some embodiments where a surface can be expected to be smoother than a surface that can be achieved using a dry etch, the silicide method shown in FIG. 6A or the gap-first dielectric method shown in FIG. 6B can be used to make a pair Electrodes and associated nano-gap.

The initial steps shown in FIG. 6A for manufacturing a device may be similar to the steps described above, where a substrate may have one or more dielectric layers deposited thereon. Then, a crystalline (epitaxial) or polycrystalline silicon layer may be deposited on the dielectric layer instead of directly depositing a metal layer on the dielectric layer. Alternatively, the substrate may be a silicon-on-insulator (SOI) wafer.

Next, an appropriate lithography process is used to pattern the silicon layer, and the silicon layer can be etched accordingly, wherein the etching method can be one of dry or wet etching described above. A silicon nitride layer may then be applied over the wafer.

Next, a polycrystalline silicon layer can be deposited, and the resulting structure can be subjected to one of the CMP procedures described above.

Next, a dielectric may be applied and an etching process (which etches the dielectric but does not significantly etch the polycrystalline silicon or silicon layer or silicon nitride layer) is used to pattern the dielectric to form a recessed area. The poly (silicon) and / or silicon layers may be intentionally etched to produce one of the grooves required to accommodate volume expansion and maintain surface flatness after silicification.

Next, a layer of platinum, titanium, or other suitable metal can be placed in the recessed area and reacted with the polycrystalline silicon layer and silicon layer using an RTA (rapid thermal annealing) procedure, where the silicide can be made of silicon and platinum, titanium, or other suitable metal form. Any remaining metal can then be removed.

An oxide layer with associated wells can be formed, and the silicon nitride layer can be etched as described above.

In other embodiments shown in FIG. 6B, a substrate having a dielectric layer (s) and a crystalline silicon top layer may be manufactured in a manner similar to the procedure described in conjunction with FIG. 6A.

Then, a dry etching or a wet etching (which uses tetramethylammonium hydroxide, KOH, or other etchant that can be etched along the crystal plane of silicon as an example) can be used to pattern the crystalline silicon.

Next, a desired layer of gold or other metal is applied and patterned as desired.

Then, one of the CMP procedures described above can be performed to planarize the surface.

An oxide layer with associated wells can be formed, and the gap can be etched to form a crystalline silicon layer as described above. Sensor electronics

Since a sensor array can be used as an integrated semiconductor device in the present invention, it exhibits great advantages in terms of accuracy, integration, and scalability. In some cases, a high data bandwidth may not be needed, especially for a system utilizing a simultaneous chemistry method. A system chip can be massively parallel and can only read a sensor that records a combined nucleotide. A chip may be mapped first to determine which sensors provide useful information and a mapping that may exist in a flash memory on a chip or may exist in other locations as part of another part of a system. This makes a system throughput (which includes data throughput) much more efficient and can help make calibration and accuracy very reliable. In some cases, a single measurement may be used. In some cases, a combined or combined labeled nucleotide may be measured multiple times until a desired accuracy is achieved.

In some cases, a sensor can be used to measure the combined and / or combined kinetic energy, so that epigenetic information can be determined as part of a certain sequence procedure, which requires multiple times and may be compared to other frequencies Read a sensor at a higher frequency. In these cases, only a portion of a chip may be utilized at a time, or a smaller chip may be utilized according to a maximum data output capability.

In some cases, a sensor may be associated with a local amplifier, such as a 4T circuit, similar to a local amplifier used in a CMOS imaging sensor. In some cases, a capacitor can be used to integrate a current generated by a tunneling electrode pair. A capacitor can be used to average changes due to binding and release of a mark from an electrode pair. A capacitor can be used to average the change in bonding position (which can cause a change in the magnitude of the current generated by an electrode pair) and to average a background (which can be derived from direct tunneling between electrodes and / or between SAM components and / Or due to other parts that can temporarily bind (such as a target DNA), unbound nucleotides, or other molecules or other contaminants that can be expected parts of a system). Such an average capacitor can be used to increase the signal-to-noise ratio and / or allow a time between measurements that is longer than when there is no capacitor, while maintaining the charge from the tunneling current.

In the case where a current combined with an integration time may be greater than a current of a magnitude and voltage associated with a charge integration capacitor, a negative gain may be used as an amplifier associated with each sensor or capacitor Part of it. Negative gain can be used, for example, when a significant change in time, location can be part of a measurement or a long time between measurements is desired for other reasons. Since it is expected that shot noise will not play an important role in a measurement, an increase in shot noise (which may originate from a negative gain) will not cause a significant decrease in the signal-to-noise ratio of a sensor.

In some cases, a gap size may be greater than or equal to about 5 nm, about 6 nm, about 7 nm, about 8 nm, about 9 nm, about 10 nm, about 15 nm, about 20 nm, about 30 nm or more . This gap size can provide additional advantages such as ease of manufacture and increased tolerance for the gap size. In these cases, a tunneling mark or tunneling and jumping mark may be configured to be larger than the gap size, such that an angle of a combined tunneling mark with respect to the surface of the first electrode opposite the second electrode may be 5 ° to 10 °, 11 ° to 20 °, 21 ° to 30 °, 31 ° to 40 °, 41 ° to 50 °, or 51 ° or more. For example, a 9 nm gap can be used with one of double-stranded DNA tags of about 30 base pairs or more. A 12 nm gap can be used with one of the double-stranded DNA tags of about 40 base pairs. A 20 nm gap can be used with one of the double-stranded DNA tags of about 60 base pairs. A gap size can be configured to fit a commercially available or easily constructed DNA oligomer of a particular length.

In some cases, a bias voltage can be turned off for most of the run while sequencing a polynucleotide. This may help to minimize the adhesion or adsorption of molecules due to static electricity, which in turn may cause artifacts, to the electrodes. In some cases, the integral solution potential can be modified during a portion of a run to minimize molecular adhesion or adsorption to the electrode. In some cases, a background signal (which can be attributed to an ion current) can be minimized due to a small exposed electrode metal surface area. In some cases, the exposed metal surface area of each sensor may be less than 1,000,000 nm ² , less than 400,000 nm ² , less than 100,000 nm ² , less than 40,000 nm ^2, or less than 10,000 nm ² . This can increase one of the signal-to-noise ratios associated with the measurement of the tunneling current. A background signal may be determined from a sensor that does not have a binding enzyme and therefore may not have a signal. In some cases, an electronic tag may be selected in a way to optimize a tunneling current. The size of one of the molecules can be selected to be slightly longer than a gap between the two tunneling electrodes (which can include a tolerance associated with the manufacture of the gap), or can be slightly longer than that (some ) A binding position associated with the SAM (which may consider changes in the binding position (s) of the SAM on the electrode and / or changes in the size of a gap between the electrodes). In some cases, a bias voltage may be used between two tunneling electrodes of a pair of tunneling electrodes, where one of the electrodes may have a positive voltage and the other of the pair of electrodes may have a voltage relative to each other One negative voltage.

In some cases, a single volume can be used as part of a single wafer so that any input fluid can interact with any of the electrode pairs on a wafer. In other cases, several volumes can be provided that can be fluidly separated, such that different fluids that can include different samples can be introduced to or separated from the volume by any fluid. The valve regulating element can be integrated as a part of a chip design, or it can provide multiple input and output ports. In some cases, different parts of a chemical action can be performed in different volumes, so that a single wafer can obtain data in a larger percentage of time. For example, if 4 fluid steps are required (each takes 1 minute) and one time required to read out a volume is 1 minute, 5 fluid volumes can be provided so that data can be obtained for one volume and 4 other volumes can be obtained Each performs a different fluid transfer. After 1 minute has elapsed, each volume can then begin a different task. Therefore, data can be continuously generated.

In some cases, one or more reference electrodes can be supplied as part of a wafer, so that the integrated fluid potential can be controlled relative to the potential of one electrode of the electrode pair. The reference electrode may be a true reference electrode, a quasi-reference electrode, a counter electrode, an auxiliary electrode, or any combination thereof. In some cases, one or more electrodes may be placed outside a wafer, for example, through a fluid line that interacts with a fluid volume having an electrode pair.

In some cases, a reference and / or counter electrode or quasi-reference electrode may be utilized in a way that makes it effectively act as a gate electrode, where, for example, a tunneling mark may have different conductances depending on the oxidation state, And a reference and / or counter electrode or quasi-electrode can be used to oxidize or reduce a mark, especially can be combined with a part of a mark of a bias or sensing electrode; the oxidation or reduction of a mark can cause a tunneling current amplitude change. Wafer fluidics

In some cases, a wafer may have a single common sampling volume such that a single input fluid, which may include input sampling, may interact with all sensors of a wafer. Alternatively, a chip may have multiple volumes associated with different sensor groups, and may have a valve adjustment mechanism or multiple input ports so that different input fluids that may include different input samples can interact with different sampling groups .

In some cases, a single input fluid may include multiple different samples. Different samples may be distinguished by having different barcodes associated with them, or different samples may have different cleavable tunneling marks attached to them. In some cases, different samples may be introduced at different times. Different samplings can occupy a portion of a different wafer area while making other sensors available for one sampling that can be introduced at a later time. After the introduction of a subsequent sampling, additional measurements (s) may be performed to measure the markers associated with or associated with the binding moiety. An additional sensor with a binding portion may be associated with a newly introduced sample and a sensor previously associated with a previous sample may still be associated with the same sample associated with one of the previous sensors. In some cases, all sensors associated with a chip may undergo different steps at the same or different times. In some cases, sampling may be introduced at different times, but other fluids may be introduced to all sensors at the same time.

In some cases, a chip can have multiple input ports associated with different internal volumes, and a system can accommodate multiple chips simultaneously. Different fluids can be introduced to different volumes at different times. Different volumes can be different volumes of a single wafer, and different volumes can be located on different wafers. Different volumes can be different volumes associated with multiple wafers, thereby allowing different steps in a procedure to occur in different volumes at different times, which can, for example, allow different volumes to be measured at different times, and equivalent at the same time When the measurement occurs, other steps can occur in other volumes. As a result, measurements can take place continuously and efficiently, thereby allowing analog-to-digital converters, integrators, digital communication channels, or any other part of an electronic device that could otherwise be a limiting factor of the system's processing capacity to be fully utilized without Limited to waiting for a chemical action, biochemical inspection, rinsing, or one or several other steps to occur. In some cases, a coordinated set of measurements may be implemented, where the measurements may not be continuous and effective, but may take place over a different step (which may be a chemical step, a biochemical step, a rinsing step, or a removal step). Any step other than a measurement step) before performing all measurements in a different area a percentage or within a duty cycle.

In some cases shown in FIG. 3Y, a wafer can have multiple fluid channels 370 that can be interconnected so that a single sample can be used, or can have separate fluid ports (not shown) so that different samples can be used for the wafer. In different sections. The sensing circuit 360, which may include an integrating capacitor, a current mirror, and an analog-to-digital converter, may be placed in a section between fluid regions that may have two groups of 100 columns or some other suitable number of columns, such that The zones can support covering fluid channels and allow the use of a much lower fluid volume. The column selection circuit 380 may be positioned on one side, and a digital input / output circuit 390 may be used which may include one or more LVDS (Low Voltage Differential Signaling) interfaces.

In some cases, a system and associated chemistry can be configured for relatively slower but more accurate detection. One of the cases can be parallelized on a large scale to improve the throughput, such as using 10M (10M), 20M, 30M, 40M, 50M, 60M, 70M, 80M, 90M, 100M 200M, 300M, 400M, 500M, 600M, 700M, 800M, 900M, 1 billion (1B), 2B, 3B, 4B, 5B, 6B, 7B , 8B, 9B, 10B, 15B, 20B or more sensors.

In some cases, different readout schemes may be employed for different regions of a device or in one or more regions of a device at different times. In some cases, one type of detection chemistry may be utilized in one or more regions or at one or more times, while a second or more additional chemistry may be utilized in other parts of a wafer.

In some cases, a field programmable gate array (FPGA) or other programmable logic within a chip may be used to allow readout patterns and / or timing changes.

In some cases, a storage device may be used to store the locations of active sites, where memory may be used as part of a readout process to determine which locations are active. A storage device can be selected as a flash memory or a ram. A storage device may be used by an on-board microprocessor or may be used in conjunction with an FPGA or other programmable logic to determine a pattern of sensor locations to be read and / or a pattern of locations not to be read. In some embodiments, different patterns may be used in different regions, and different timings may be used between readings, such as when one region is used for a chemical reading and another region is used for a different chemical reading. Tunneling and electrochemical marking

As provided herein, a tunneling tag can be a compound through which a tunneling current can provide a large number of electrons from a single polymer molecule with a low background level. For example, a current of 1 nA can generate 6.2M electrons in 1 second. If there is a background of 5 pA, this can result in a shot noise of> 1000: 1 limiting the S / N level.

In some cases, a tunneling mark may provide a value corresponding to less than 10-11, 10-11 to 10-10, 10-10 to 10-9, 10-9 to 10-8, or 10-8 to 10-7 or More Siemens conductance current. Therefore, a nominal bias potential, such as less than 10 mV, 10 mV to 100 mV, 100 mV to 250 mV, or greater than 250 mV, can be used to generate effective current, making shot noise insignificant in many systems. of.

In some cases, an electron or hole that interacts with a tunneling mark may tunnel into or pass through a tunneling mark, and may hop through a tunneling mark. Electrons or holes can tunnel through a portion of a tunneling mark and hop through other portions of a tunneling mark. Electrons or holes can repeatedly transition between some areas of a tunneling mark where tunneling can occur and areas where jumps can occur. An exemplary mark 402 for use with a pair of electrodes 401A and 401B is shown in FIG. 4.

In some cases, electrochemical labels can be utilized. Electrochemical labeling can be utilized so that a binding nucleotide can generate a current due to oxidation and reduction at two different electrodes of an electrode pair, which can maintain the electrode pair at a voltage suitable for oxidation and reduction. In some cases, an identical electrochemical label can be used for more than one type of nucleotide. A diffusion difference may cause different nucleotide types to produce a different average current due to, for example, different diffusion rates of different nucleotides. Different diffusion rates may result from associating a same electrochemical label with different additional portions. Different additional portions may be non-electrochemically active. Different additional portions can slow the diffusion of an electrochemical label that can be bonded to a nucleotide.

In some cases, different tunneling and / or electrochemical labels may be utilized, and one current associated with an electrode pair may be measured at different times. A potential other than the integral solution potential can be used for one or both electrodes, so that the currents associated with different electrode pairs can be used to distinguish different electrochemical labels.

In some cases, more than one electrode pair may be utilized. More than one electrode pair can be associated with an enzyme binding site, so that more than one electrode pair can be accessed by a labeled nucleotide. A labeled nucleotide (e.g., a label associated with a nucleotide) can be bound by an enzyme. Different electrode pairs can place one or both electrodes at a different potential than the integrated solution, so that the currents associated with different electrode pairs can be used to distinguish between different tunneling and / or electrochemical labels.

In some cases, a combination of one of multiple sets of different electrodes may be used such that the currents associated with different electrode pairs can be used to distinguish between different tunneling and / or electrochemical labels. Different nucleotides that may have an identical tunneling and / or electrochemical label may further include one or more additional moieties such as nucleic acids and / or proteins. One or more additional portions may or may not be the same. In some cases, one or more of the additional portions may be different, such that a same electrochemical label may have different diffusion rates and thus different currents. Sensor Chip: General Purpose

In some cases, the system and method of the present invention may utilize a chip. A wafer may include a reusable wafer. A wafer may have at least some target analytes, enzymes, and SAM removed between different runs. Removal can be performed by, for example, increasing temperature, reducing ion concentration, chemical cleaning, plasma cleaning, enzyme cleaning, electrode potential cleaning, any other type of cleaning procedure, or a combination thereof. This wash may include a nuclease, a protease, such as proteinase K. Cleaning may include changing the potential between the electrode and the body solution so that the thiolated SAM can be removed or any other method can be utilized.

In some cases, one of the systems described herein can be used for DNA sequencing, RNA sequencing, and can be measured or interrogated more than once, depending on the application, and when deemed to be helpful for the overall accuracy of a particular measurement. In some cases, a system may use a single sample to perform one or more tasks, including sequencing DNA, sequencing RNA, determining epigenetics of DNA with or without chemical modification, determining whether or not Epigenetics of RNA without chemical modification, determination of the number of DNA copies (including determination of aneuploidy), determination of the expression of different transcriptions, determination of the presence and number of different proteins, and determination of Existence and quantity.

In some cases, a system may include a wafer with an electrode structure, and may not include an amplifier or column and / or row selection associated with different sensors. The circuit required for measurement may not be part of a chip, but may be part of an additional chip or circuit. In other cases, the local amplifier and the optional column and / or row selection circuit may include a part of a chip, and the integration, dual correlation, category-to-digital conversion, and digital input and output ports may not be part of the chip, but may be a Part of an extra chip or circuit.

Although the preferred embodiments of the invention have been shown and described herein, those skilled in the art will appreciate that these embodiments are for illustration only. Those skilled in the art will now think of many variations, changes, and substitutions without departing from the invention. It should be understood that various alternatives to the embodiments of the invention described herein may be employed in practicing the invention. The following patent applications are intended to define the scope of the present invention and thereby encompass methods and structures within the scope of this patent application and its equivalents.

101‧‧‧ substrate

102‧‧‧First dielectric layer

103‧‧‧Second dielectric layer

104‧‧‧first photoresist layer

105‧‧‧Second photoresist layer

106‧‧‧ first metallization layer

107‧‧‧Second metallization layer

108‧‧‧ Dielectric layer

109‧‧‧ Third metallization layer

110‧‧‧ oxide layer

111‧‧‧Second oxide layer

201‧‧‧ substrate

202‧‧‧First dielectric layer

203‧‧‧Second dielectric layer

204‧‧‧ inverted cone layer

205‧‧‧first metallization layer

206‧‧‧ Dielectric layer

207‧‧‧Second metallization layer

208‧‧‧oxide layer

209‧‧‧Second oxide layer

330‧‧‧ Polymerase / Other Enzymes

340‧‧‧inclined surface

342A‧‧‧electrode

342B‧‧‧electrode

360‧‧‧sensing circuit

370‧‧‧fluid channel

380‧‧‧column selection circuit

390‧‧‧Digital input and output circuit

401A‧‧‧electrode

401B‧‧‧electrode

402‧‧‧Mark

The novel features of the invention are clearly set forth in the scope of the accompanying patent application. A better understanding of the features and advantages of the present invention will be achieved by referring to the [implementation] of the illustrative embodiment (where the principle of the present invention is used) and the following drawings:

1A to 1K show steps of a method for manufacturing a pair of nano-electrodes associated with a nano-gap sensor;

2A to 2M show steps of another manufacturing method of a pair of nanometer electrodes associated with a nanometer gap sensor;

3A to 3D show steps of another method of manufacturing a pair of nano-electrodes associated with a nano-gap sensor;

3E to 3I show SEM and TEM images of a sensor formed using the procedures shown in FIGS. 3A to 3D;

3J and 3K show another method for forming a nano-gap sensor;

3L to 3N show another method for forming a nano-gap sensor;

3O to 3V show another method for forming a nano-gap sensor;

FIG. 3W depicts a nano-gap sensor having a narrower nano-gap;

Figure 3Y shows one of the wafers with multiple fluid paths for the sensor array and associated circuits;

Figure 4 shows a nano-gap sensor used with a tunneling mark; and

FIG. 5 shows a TEM of a first metallization layer; and

6A to 6B show different manufacturing methods of a nano-gap sensor having a smooth electrode surface.

Claims (28)

A method comprising: a. Using a polymerase adjacent to two electrodes on a substrate to bind a nucleotide complementary to an interrogated base of a sampled nucleic acid, the nucleotide having a nucleotide attached to it A tunneling mark; b. Measuring a tunneling current between the two electrodes caused by positioning the tunneling mark to the two electrodes; and c. Self-complementary based on the tunneling current measurement Base binding to the interrogated base recognizes a nucleotide. The method of claim 1, wherein the tunneling mark is slightly larger than a gap between the two electrodes. The method of claim 2, wherein the tunneling marker comprises a zwitterionic compound. The method of claim 1, wherein the tunneling marker comprises a nucleic acid strand. The method of claim 4, wherein the nucleic acid strand is longer than 10 bases. The method of claim 4, wherein the nucleic acid strand has a double-stranded portion and a single-stranded portion. The method of claim 1, further binding the polymerase to a dielectric between the two electrodes. The method of claim 1, further binding the polymerase to one of the two electrodes. The method of claim 1, wherein the gap has a wider portion larger than a width of the polymerase and a smaller portion smaller than a size of the polymerase. The method of claim 1, wherein a self-assembled monolayer is bonded to the electrodes. The method of claim 10, wherein the self-assembled monolayer is bonded to the electrodes by a thiol group. The method of claim 4 or 10, wherein the self-assembling monolayer at least partially comprises a nucleic acid that can bind to at least a portion of the tunneling labeled nucleic acid strand. The method of claim 12, wherein the combination is temporary. As in the method of claim 13, wherein the temporary binding can occur more frequently than the binding occurring in the absence of high local concentration due to the binding of the nucleobase to one of the tunneling markers attached thereto. The method of claim 1, wherein the tunneling tag is bound to 5 'of the ribose of the nucleobase. The method of claim 1, wherein the tunneling tag is bound to a base of the nucleobase. The method of claim 1, wherein the nucleobase further comprises a terminator. The method of claim 17, wherein the terminator is bound to 3 'of the ribose. The method of claim 15 wherein the method is a simultaneous chemical method. A device comprising: a. Two electrodes, which are disposed on a substrate, separated by a non-conductive gap; b. The two electrodes and the gap configured to accommodate a polymerase near the two electrodes C. The two electrodes and the gap are further configured to detect a tunneling current due to at least one of a combination and combination of a nucleotide and a tunneling marker, the tunneling marker and a sampling One of the nucleic acids asks for base complementarity. The device of claim 20, which is further configured to place the polymerase in the non-conductive gap, wherein the gap is etched down between the electrodes to a depth of 10 nm or more. If the device of claim 21 is further configured such that the size of the non-conductive gap is smaller than one of the polymerases and configured to position the polymerase above the non-conductive gap, the non-conductive gap can be etched to 10 nm or A smaller depth. The device of claim 20, wherein the non-conductive gap has a wider portion and a narrower portion. A method comprising: a. Binding a nucleobase using a polymerase adjacent to two electrodes on a substrate, the nucleobase having a tunneling tag attached to the nucleobase, the tunneling tag and a sampling One of the nucleic acids interrogates base complementation; b. Measures a combination of at least one of a tunneling current and a jump current between the two electrodes caused by positioning the tunneling marker to the two electrodes; c. Based on Electronic current measurement to identify one matching nucleobase on a single strand of a polynucleotide. A method for finding biological information associated with a nucleic acid polymer, the method comprising: a. Positioning the nucleic acid polymer between two electrodes on a substrate, wherein the positioning is performed by hydrogen bonding; b Applying a bias voltage between the two electrodes; c. Measuring a tunneling current between the two electrodes; d. Determining the biological information based on conductance. The method of claim 25, wherein the length of the nucleic acid polymer is less than or equal to the size of a gap between the two electrodes. The method of claim 25, wherein the length of the nucleic acid polymer is greater than the size of a gap between the two electrodes and wherein a part of the oligomer is hybridized to either or both of the electrodes, and One part of the oligomer spans a gap between the two electrodes. The method of claim 25, wherein a specific measured conductance indicates methylation at a specific site on the oligomer.