TW202510016A - 包含電荷捕捉層之載體、包含該載體之相關複合基板及相關製造方法 - Google Patents
包含電荷捕捉層之載體、包含該載體之相關複合基板及相關製造方法 Download PDFInfo
- Publication number
- TW202510016A TW202510016A TW113105900A TW113105900A TW202510016A TW 202510016 A TW202510016 A TW 202510016A TW 113105900 A TW113105900 A TW 113105900A TW 113105900 A TW113105900 A TW 113105900A TW 202510016 A TW202510016 A TW 202510016A
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- carrier
- sprt
- dielectric constant
- composite substrate
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1914—Preparing SOI wafers using bonding
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/01—Manufacture or treatment
- H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
- H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1914—Preparing SOI wafers using bonding
- H10P90/1918—Preparing SOI wafers using bonding including charge trapping layers, e.g. polycrystalline materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
- H10P14/6326—Deposition processes
- H10P14/6328—Deposition from the gas or vapour phase
- H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
- H10P14/665—Porous materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/69—Inorganic materials
- H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
- H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
- H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Solid-Sorbent Or Filter-Aiding Compositions (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Filtering Materials (AREA)
- Laminated Bodies (AREA)
- Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
- Formation Of Insulating Films (AREA)
- Recrystallisation Techniques (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR2301532A FR3146020B1 (fr) | 2023-02-20 | 2023-02-20 | Support comprenant une couche de piégeage de charges, substrat composite comprenant un tel support et procédé de fabrication associés |
| FR2301532 | 2023-02-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW202510016A true TW202510016A (zh) | 2025-03-01 |
Family
ID=86942201
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW113105900A TW202510016A (zh) | 2023-02-20 | 2024-02-20 | 包含電荷捕捉層之載體、包含該載體之相關複合基板及相關製造方法 |
Country Status (7)
| Country | Link |
|---|---|
| EP (1) | EP4670206A1 (fr) |
| JP (1) | JP2026506712A (fr) |
| KR (1) | KR20250152578A (fr) |
| CN (1) | CN121175796A (fr) |
| FR (1) | FR3146020B1 (fr) |
| TW (1) | TW202510016A (fr) |
| WO (1) | WO2024175311A1 (fr) |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2860341B1 (fr) | 2003-09-26 | 2005-12-30 | Soitec Silicon On Insulator | Procede de fabrication de structure multicouche a pertes diminuees |
| FR2953640B1 (fr) | 2009-12-04 | 2012-02-10 | S O I Tec Silicon On Insulator Tech | Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante |
| FR2973159B1 (fr) | 2011-03-22 | 2013-04-19 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat de base |
| FR2973158B1 (fr) | 2011-03-22 | 2014-02-28 | Soitec Silicon On Insulator | Procédé de fabrication d'un substrat de type semi-conducteur sur isolant pour applications radiofréquences |
| US9768056B2 (en) | 2013-10-31 | 2017-09-19 | Sunedison Semiconductor Limited (Uen201334164H) | Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition |
| FR3024587B1 (fr) * | 2014-08-01 | 2018-01-26 | Soitec | Procede de fabrication d'une structure hautement resistive |
| US9853133B2 (en) | 2014-09-04 | 2017-12-26 | Sunedison Semiconductor Limited (Uen201334164H) | Method of manufacturing high resistivity silicon-on-insulator substrate |
| US9899499B2 (en) | 2014-09-04 | 2018-02-20 | Sunedison Semiconductor Limited (Uen201334164H) | High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss |
| US10312134B2 (en) | 2014-09-04 | 2019-06-04 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss |
| WO2016081367A1 (fr) | 2014-11-18 | 2016-05-26 | Sunedison Semiconductor Limited | Substrat de silicium sur isolant de grande résistivité comprenant une couche de piégeage de charge formée par co-implantation he-n2 |
| EP4120320A1 (fr) | 2015-03-03 | 2023-01-18 | GlobalWafers Co., Ltd. | Films de silicium polycristallin de piégeage de charge sur des substrats de silicium avec une contrainte de film commandable |
| CN107408532A (zh) | 2015-03-17 | 2017-11-28 | 太阳能爱迪生半导体有限公司 | 用于绝缘体上半导体结构的制造的热稳定电荷捕获层 |
| FR3048306B1 (fr) | 2016-02-26 | 2018-03-16 | Soitec | Support pour une structure semi-conductrice |
| CN115714130A (zh) | 2016-12-05 | 2023-02-24 | 环球晶圆股份有限公司 | 高电阻率绝缘体上硅结构及其制造方法 |
| WO2019111893A1 (fr) * | 2017-12-06 | 2019-06-13 | 株式会社村田製作所 | Dispositif à ondes acoustiques |
| US11164740B2 (en) | 2019-10-09 | 2021-11-02 | Newport Fab, Llc | Semiconductor structure having porous semiconductor layer for RF devices |
| FR3104318B1 (fr) | 2019-12-05 | 2023-03-03 | Soitec Silicon On Insulator | Procédé de formation d'un support de manipulation à haute résistivité pour substrat composite |
| JP7400634B2 (ja) * | 2020-06-09 | 2023-12-19 | 信越半導体株式会社 | Soi基板及びsoi基板の製造方法 |
-
2023
- 2023-02-20 FR FR2301532A patent/FR3146020B1/fr active Active
-
2024
- 2024-01-30 WO PCT/EP2024/052134 patent/WO2024175311A1/fr not_active Ceased
- 2024-01-30 JP JP2025547938A patent/JP2026506712A/ja active Pending
- 2024-01-30 CN CN202480011958.2A patent/CN121175796A/zh active Pending
- 2024-01-30 EP EP24703123.0A patent/EP4670206A1/fr active Pending
- 2024-01-30 KR KR1020257026470A patent/KR20250152578A/ko active Pending
- 2024-02-20 TW TW113105900A patent/TW202510016A/zh unknown
Also Published As
| Publication number | Publication date |
|---|---|
| CN121175796A (zh) | 2025-12-19 |
| KR20250152578A (ko) | 2025-10-23 |
| JP2026506712A (ja) | 2026-02-25 |
| FR3146020B1 (fr) | 2025-07-18 |
| EP4670206A1 (fr) | 2025-12-31 |
| WO2024175311A1 (fr) | 2024-08-29 |
| FR3146020A1 (fr) | 2024-08-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN114127893B (zh) | 制造包括转移到设置有电荷俘获层的支撑体上的薄层的结构的方法 | |
| TWI758133B (zh) | 製備多層結構的方法 | |
| CN107533953B (zh) | 具有可控膜应力的在硅衬底上沉积电荷捕获多晶硅膜的方法 | |
| CN114556526B (zh) | 形成用于复合衬底的高电阻率处理支撑体的方法 | |
| JP2026511205A (ja) | 電荷トラップ層を含む支持体、そのような支持体を含む複合基板、および関連する製造方法 | |
| JP2026511206A (ja) | 電荷トラップ層を含む支持体、そのような支持体を含む複合基板、および関連する製造方法 | |
| JP7230297B2 (ja) | 集積された高周波デバイスのための基板及びそれを製造するための方法 | |
| JP2026511208A (ja) | 電荷トラップ層を含む支持体、そのような支持体を含む複合基板、および関連する製造方法 | |
| US8343850B2 (en) | Process for fabricating a substrate comprising a deposited buried oxide layer | |
| KR20250036825A (ko) | 원자종의 확산을 방지하기 위한 장벽층을 포함하는 구조체 제조 방법 | |
| TW202510016A (zh) | 包含電荷捕捉層之載體、包含該載體之相關複合基板及相關製造方法 | |
| JP2023530850A (ja) | Soi構造用キャリア基板及び関連付けられた製造方法 | |
| TW202445754A (zh) | 包含表面層之結構及其製作方法,該表面層係接合至具有限污染之電荷捕捉層的載體上 | |
| TW202416352A (zh) | 用於製作具原子物種擴散阻隔層之結構之方法 | |
| CN120826778A (zh) | 包括厚掩埋介电层的基板和制备这种基板的方法 | |
| TW202507818A (zh) | 用於製備鐵電材料薄層之方法 |