TW296474B - - Google Patents
Download PDFInfo
- Publication number
- TW296474B TW296474B TW085103887A TW85103887A TW296474B TW 296474 B TW296474 B TW 296474B TW 085103887 A TW085103887 A TW 085103887A TW 85103887 A TW85103887 A TW 85103887A TW 296474 B TW296474 B TW 296474B
- Authority
- TW
- Taiwan
- Prior art keywords
- bonding
- input
- semiconductor
- distance
- integrated circuit
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
- H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/547—Dispositions of multiple bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/59—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Wire Bonding (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP08043195A JP3557708B2 (ja) | 1995-04-05 | 1995-04-05 | 半導体集積回路装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW296474B true TW296474B (ja) | 1997-01-21 |
Family
ID=13718088
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW085103887A TW296474B (ja) | 1995-04-05 | 1996-04-02 |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP3557708B2 (ja) |
| TW (1) | TW296474B (ja) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3274633B2 (ja) | 1997-09-29 | 2002-04-15 | ローム株式会社 | 半導体集積回路装置 |
| JP6100648B2 (ja) | 2013-08-28 | 2017-03-22 | ルネサスエレクトロニクス株式会社 | 半導体装置及び半導体装置の製造方法 |
-
1995
- 1995-04-05 JP JP08043195A patent/JP3557708B2/ja not_active Expired - Fee Related
-
1996
- 1996-04-02 TW TW085103887A patent/TW296474B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| JP3557708B2 (ja) | 2004-08-25 |
| JPH08279527A (ja) | 1996-10-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6150710A (en) | Transverse hybrid LOC package | |
| TW510034B (en) | Ball grid array semiconductor package | |
| TW409328B (en) | Semiconductor integrated circuit device having dummy bonding wires | |
| TW575951B (en) | Semiconductor device | |
| TW463346B (en) | Dual-leadframe package structure and its manufacturing method | |
| TW293167B (ja) | ||
| US5164817A (en) | Distributed clock tree scheme in semiconductor packages | |
| US5757082A (en) | Semiconductor chips, devices incorporating same and method of making same | |
| US6509632B1 (en) | Method of fabricating a redundant pinout configuration for signal enhancement in an IC package | |
| US6121690A (en) | Semiconductor device having two pluralities of electrode pads, pads of different pluralities having different widths and respective pads of different pluralities having an aligned transverse edge | |
| JP2809945B2 (ja) | 半導体装置 | |
| TW567602B (en) | Multi-chip module | |
| TW296474B (ja) | ||
| TW441053B (en) | Semiconductor chip package with multilevel leads | |
| KR20010037246A (ko) | 리드프레임 및 이를 이용한 반도체패키지 | |
| TW469610B (en) | Package structure having testing pads on chip | |
| JPS59139660A (ja) | 半導体装置 | |
| CN221960969U (zh) | 引线框架和封装体 | |
| WO1993017455A2 (en) | Integrated-circuit package configuration for packaging an integrated-circuit die and method of packaging an integrated-circuit die | |
| KR0137068B1 (ko) | 리드 프레임 | |
| TW516192B (en) | Semiconductor device having lead terminal on only one side of a package | |
| US6621150B1 (en) | Lead frame adaptable to the trend of IC packaging | |
| TW506104B (en) | Pad structure of input/output unit and the layout method thereof | |
| JPH02219257A (ja) | マルチチップ型半導体装置とその製造方法 | |
| TW594970B (en) | Semiconductor device, method for manufacturing same and portable device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |