TW356559B - Method for fabricating semiconductor devices having triple well - Google Patents

Method for fabricating semiconductor devices having triple well

Info

Publication number
TW356559B
TW356559B TW086115298A TW86115298A TW356559B TW 356559 B TW356559 B TW 356559B TW 086115298 A TW086115298 A TW 086115298A TW 86115298 A TW86115298 A TW 86115298A TW 356559 B TW356559 B TW 356559B
Authority
TW
Taiwan
Prior art keywords
type well
type
silicon substrate
mask
impurity ions
Prior art date
Application number
TW086115298A
Other languages
Chinese (zh)
Inventor
Dae-Yong Shim
Byeong-Ryeol Lee
Original Assignee
Hyundai Electronics Ind
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Ind filed Critical Hyundai Electronics Ind
Application granted granted Critical
Publication of TW356559B publication Critical patent/TW356559B/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0191—Manufacturing their doped wells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

A kind of method for fabricating a semiconductor having triple wells, it comprises the following steps: an element isolation mask formed on a P-type silicon substrate; forming a N-type well mask on the element isolation mask; to implant N-type impurity ions in the exposed portion of the semiconductor substrate, N-type well implant region is formed in this way; removing the N-well mask, and oxidizing the silicon substrate portion of the corresponding field region, meanwhile according to the thermal oxidation process, infiltrating the N-type impurity ions of the N-type well implanting region into the semiconductor substrate, thereby forming field oxide film and defused N-type well portion; a P-type well mask formed on the silicon substrate, whereas the element isolation mask remained on the substrate; and implanting P-type impurity ions in the exposed portion of the silicon substrate, on the other hand in the meantime varying the concentration of the P-type impurity ions and ion implantation energy, therefore forming a P-type well regions in the silicon substrate, and forming internal p-type well portion in the N-type well portion.
TW086115298A 1996-12-31 1997-10-17 Method for fabricating semiconductor devices having triple well TW356559B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960080269A KR100220954B1 (en) 1996-12-31 1996-12-31 Method of manufacturing a semiconductor device having a triple well

Publications (1)

Publication Number Publication Date
TW356559B true TW356559B (en) 1999-04-21

Family

ID=19493519

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086115298A TW356559B (en) 1996-12-31 1997-10-17 Method for fabricating semiconductor devices having triple well

Country Status (4)

Country Link
JP (1) JP2998730B2 (en)
KR (1) KR100220954B1 (en)
GB (1) GB2320802B (en)
TW (1) TW356559B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100328455B1 (en) * 1997-12-30 2002-08-08 주식회사 하이닉스반도체 Method of manufacuring a semiconductor device
KR100465606B1 (en) * 1998-06-30 2005-04-06 주식회사 하이닉스반도체 Triple well manufacturing method of semiconductor device
KR100524465B1 (en) * 2003-06-30 2005-10-26 주식회사 하이닉스반도체 Method of manufacturing in semiconductor device
WO2013164210A1 (en) 2012-05-02 2013-11-07 Elmos Semiconductor Ag Pmos transistor having low threshold voltage and method for the production thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2795565B2 (en) * 1991-10-08 1998-09-10 シャープ株式会社 Method for manufacturing semiconductor storage element
US5702988A (en) * 1996-05-02 1997-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Blending integrated circuit technology

Also Published As

Publication number Publication date
JPH10209295A (en) 1998-08-07
KR19980060901A (en) 1998-10-07
KR100220954B1 (en) 1999-09-15
GB9722437D0 (en) 1997-12-24
GB2320802A (en) 1998-07-01
GB2320802B (en) 2002-01-30
JP2998730B2 (en) 2000-01-11

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees