TW358917B - A circuit and method for overflow detection in a digital signal processor having a barrel shifter and arithmetic logic unit connected in series - Google Patents

A circuit and method for overflow detection in a digital signal processor having a barrel shifter and arithmetic logic unit connected in series

Info

Publication number
TW358917B
TW358917B TW086113031A TW86113031A TW358917B TW 358917 B TW358917 B TW 358917B TW 086113031 A TW086113031 A TW 086113031A TW 86113031 A TW86113031 A TW 86113031A TW 358917 B TW358917 B TW 358917B
Authority
TW
Taiwan
Prior art keywords
logic unit
arithmetic logic
overflow
operand
digital signal
Prior art date
Application number
TW086113031A
Other languages
English (en)
Inventor
Min-Joong Rim
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Application granted granted Critical
Publication of TW358917B publication Critical patent/TW358917B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905—Exception handling
    • G06F7/4991—Overflow or underflow
    • G06F7/49921—Saturation, i.e. clipping the result to a minimum or maximum value

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Complex Calculations (AREA)
  • Executing Machine-Instructions (AREA)
TW086113031A 1997-01-16 1997-09-09 A circuit and method for overflow detection in a digital signal processor having a barrel shifter and arithmetic logic unit connected in series TW358917B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970001122A KR100236533B1 (ko) 1997-01-16 1997-01-16 배럴 쉬프터와 산술논리 연산기가 연결되어 있는 디지탈 신호 처리기 및 그 오버플로 검출방법

Publications (1)

Publication Number Publication Date
TW358917B true TW358917B (en) 1999-05-21

Family

ID=19494824

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086113031A TW358917B (en) 1997-01-16 1997-09-09 A circuit and method for overflow detection in a digital signal processor having a barrel shifter and arithmetic logic unit connected in series

Country Status (4)

Country Link
US (1) US5907498A (zh)
KR (1) KR100236533B1 (zh)
DE (1) DE19748484B4 (zh)
TW (1) TW358917B (zh)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2772946B1 (fr) * 1997-12-23 2004-01-30 Sgs Thomson Microelectronics Procede de determination d'un depassement de format du resultat d'une operation arithmetique realisee sur deux operandes
US7206800B1 (en) * 2000-08-30 2007-04-17 Micron Technology, Inc. Overflow detection and clamping with parallel operand processing for fixed-point multipliers
US6912560B2 (en) * 2000-12-08 2005-06-28 Agere Systems, Inc. Adder with improved overflow flag generation
EP1387259B1 (en) * 2002-07-31 2017-09-20 Texas Instruments Incorporated Inter-processor control
EP1503280A1 (en) * 2003-07-30 2005-02-02 Texas Instruments Incorporated Saturated arithmetic in a processing unit
AT413895B (de) * 2003-09-08 2006-07-15 On Demand Informationstechnolo Digitale signalverarbeitungseinrichtung
US8719837B2 (en) * 2004-05-19 2014-05-06 Synopsys, Inc. Microprocessor architecture having extendible logic
US7454455B2 (en) * 2004-06-07 2008-11-18 International Business Machines Corporation Apparatus, and system, for efficient and reliable computation of results for mathematical functions
US8209366B2 (en) * 2005-02-28 2012-06-26 Hitachi Global Storage Technologies Netherlands B.V. Method, apparatus and program storage device that provides a shift process with saturation for digital signal processor operations
US20070005676A1 (en) * 2005-06-29 2007-01-04 Henry Matthew R Simple and amended saturation for pipelined arithmetic processors
US20070073925A1 (en) * 2005-09-28 2007-03-29 Arc International (Uk) Limited Systems and methods for synchronizing multiple processing engines of a microprocessor
KR101471227B1 (ko) * 2010-05-28 2014-12-10 충북대학교 산학협력단 일진법 수의 데이터 처리 장치 및 이를 이용한 연산 방법
US9449607B2 (en) * 2012-01-06 2016-09-20 Qualcomm Incorporated Systems and methods for detecting overflow
US9478312B1 (en) 2014-12-23 2016-10-25 Amazon Technologies, Inc. Address circuit

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0202633B1 (en) * 1985-05-17 1991-01-23 Nec Corporation Processing circuit capable of raising throughput of accumulation
US5231600A (en) * 1990-04-19 1993-07-27 Bull Hn Information Systems Inc. Overflow detector for anticipating producing invalid operands resulting from performing shift operations on such operands
JP2894015B2 (ja) * 1991-06-28 1999-05-24 日本電気株式会社 桁あふれ検出方法および回路
JP3487903B2 (ja) * 1993-11-12 2004-01-19 松下電器産業株式会社 演算装置及び演算方法
FR2718864B1 (fr) * 1994-04-19 1996-05-15 Sgs Thomson Microelectronics Dispositif de traitement numérique avec instructions de recherche du minimum et du maximum.
JP2789577B2 (ja) * 1995-02-07 1998-08-20 日本電気株式会社 加算オーバフロ検出回路

Also Published As

Publication number Publication date
DE19748484A1 (de) 1998-07-23
KR100236533B1 (ko) 2000-01-15
KR19980065904A (ko) 1998-10-15
DE19748484B4 (de) 2010-10-07
US5907498A (en) 1999-05-25

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Legal Events

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MM4A Annulment or lapse of patent due to non-payment of fees